VxWorks Reference Manual : Libraries
excArchLib - architecture-specific exception-handling facilities
excVecInit( ) - initialize the exception/interrupt vectors
excConnect( ) - connect a C routine to an exception vector (PowerPC)
excIntConnect( ) - connect a C routine to an asynchronous exception vector (PowerPC, ARM)
excCrtConnect( ) - connect a C routine to a critical exception vector (PowerPC 403)
excIntCrtConnect( ) - connect a C routine to a critical interrupt vector (PowerPC 403)
excVecSet( ) - set a CPU exception vector (PowerPC, ARM)
excVecGet( ) - get a CPU exception vector (PowerPC, ARM)
This library contains exception-handling facilities that are architecture dependent. For information about generic (architecture-independent) exception-handling, see the manual entry for excLib.
excLib.h
excArchLib, excLib, dbgLib, sigLib, intLib
excVecInit( ) - initialize the exception/interrupt vectors
STATUS excVecInit (void)
This routine sets all exception vectors to point to the appropriate default exception handlers. These handlers will safely trap and report exceptions caused by program errors or unexpected hardware interrupts.
- MC680x0:
- All vectors from vector 2 (address 0x0008) to 255 (address 0x03fc) are initialized. Vectors 0 and 1 contain the reset stack pointer and program counter.
All vectors from 0 (offset 0x000) through 255 (offset 0xff0) are initialized.
i960: The i960 fault table is filled with a default fault handler, and all non-reserved vectors in the i960 interrupt table are filled with a default interrupt handler.
All MIPS exception, trap, and interrupt vectors are set to default handlers.
i386/i486: All vectors from vector 0 (address (0x0000) to 255 (address 0x07f8) are initialized to default handlers.
PowerPC: There are 48 vectors and only vectors that are used are initialized.
SH702x/SH703x/SH704x/SH7604: All vectors from 4 (offset 0x10) through 10 (offset 0x28), and 12 (offset 0x30) through 63 (offset 0xfc) are filled with the default exception handler. NMI vector 11 (offset 0x2c), and all vectors from 64 (offset 0x100) through 127 (offset 0x1fc) are filled with the uninitialized interrupt handler. For SH704x processors, all vectors from 128 (offset 0x200) through 255 (offset 0x3fc) are also filled with the uninitialized interrupt handler. Vectors 0 and 1 contain the power-on reset program counter and stack pointer. Vectors 2 and 3 contain the manual reset program counter and stack pointer.
SH770x: SH770x processors define exception codes (12bits, interleaved by 0x20) to specify exception events. VxWorks for SH770x locates a vector table at (vbr + 0x800), and defines vector offsets as (exception codes / 8). This vector table is commonly used by all exceptions, interrupts, and software traps. The exception dispatch code is loaded to (vbr + 0x100), and the TLB mishit exception handler is loaded to (vbr + 0x400). The exception dispatch code fetches an exception code from EXPEVT register, and it calculates the vector offset and jumps to an individual exception handler. For software trap by "trapa #imm" instruction, SH770x processors set TRA register with a value of (imm << 2). The exception dispatch code uses this TRA register value as the vector offset to the same vector table. All vectors for exception code 0x0 (offset 0x0) through 0x1a0 (offset 0x34), and 0x1e0 (offset 0x3c) are filled with the default exception handler. Vector for NMI event code 0x1c0 (offset 0x38), and all vectors for exception code 0x200 (offset 0x40) through 0xfe0 (offset 0x1fc) are filled with the uninitialized interrupt handler. Also, all vectors for "trapa #128" (offset 0x200) through "trapa #255" (offset 0x3fc) are filled with the default exception handler. SH770x processors define the exception code 0x0 as power-on reset, and 0x20 as manual reset, with execution vectoring to address 0xa0000000. Thus the first two entries in the vector table are not used for these reset exceptions. VxWorks for SH770x uses these two vectors for special purposes, "trapa #0" (offset 0x0) to implement software breakpoint, and "trapa #1' (offset 0x4) to detect integer zero divide exception.
All exception vectors are initialized to default handlers except 0x14 (Address) which is now reserved on the ARM and 0x1C (FIQ), which is not used by VxWorks.
This routine is usually called from the system start-up routine, usrInit( ), in usrConfig.c. It must be called before interrupts are enabled. (SPARC: It must also be called when the system runs with the on-chip windows (no stack)).
The SH on-chip bus state controller (BSC) does not have a mechanism to detect a bus timeout error exception, thus it is not possible to detect an access error to a non-existent memory address on cpu's local bus. However, an external bus controller may have an ability to detect the bus timeout error for an external bus access, and it may report it to CPU using interrupt mechanism. To handle this bus timeout error interrupt as an exception, the SH version of excVecInit( ) requires a global variable sysBErrVecNum in BSP, with an appropriate interrupt number as the initial value. The NMI (Non-Maskable Interrupt) is typically used for this purpose. If sysBErrVecNum has a valid interrupt vector number as its value, excVecInit( ) overrides the corresponding interrupt vector with a special bus error handler. This handler requires a BSP routine "void sysBErrIntAck (void)" to acknowledge the bus error interrupt. Then the bus error interrupt is treated as an exception, and the handler runs in the context of offending task. If the bus timeout interrupt is not available on your system, sysBErrVecNum should be set to NONE (-1).
OK, always.
excConnect( ) - connect a C routine to an exception vector (PowerPC)
STATUS excConnect ( VOIDFUNCPTR * vector, /* exception vector to attach to */ VOIDFUNCPTR routine /* routine to be called */ )
This routine connects a specified C routine to a specified exception vector. An exception stub is created and in placed at vector in the exception table. The address of routine is stored in the exception stub code. When an exception occurs, the processor jumps to the exception stub code, saves the registers, and calls the C routines.
The routine can be any normal C code, except that it must not invoke certain operating system functions that may block or perform I/O operations.
The registers are saved to an Exception Stack Frame (ESF) placed on the stack of the task that has produced the exception. The structure of the ESF used to save the registers is defined in h/arch/ppc/esfPpc.h.
The only argument passed by the exception stub to the C routine is a pointer to the ESF containing the registers values. The prototype of this C routine is described below:
void excHandler (ESFPPC *);When the C routine returns, the exception stub restores the registers saved in the ESF and continues execution of the current task.
OK, always.
excArchLib, excIntConnect( ), excVecSet( )
excIntConnect( ) - connect a C routine to an asynchronous exception vector (PowerPC, ARM)
STATUS excIntConnect ( VOIDFUNCPTR * vector, /* exception vector to attach to */ VOIDFUNCPTR routine /* routine to be called */ )
This routine connects a specified C routine to a specified asynchronous exception vector.
When the C routine is invoked, interrupts are still locked. It is the responsibility of the C routine to re-enable the interrupt.
The routine can be any normal C code, except that it must not invoke certain operating system functions that may block or perform I/O operations.
On PowerPC, the vector is typically the external interrupt vector 0x500 and the decrementer vector 0x900. An interrupt stub is created and placed at vector in the exception table. The address of routine is stored in the interrupt stub code. When the asynchronous exception occurs the processor jumps to the interrupt stub code, saves only the requested registers, and calls the C routines.
Before saving the requested registers, the interrupt stub switches from the current task stack to the interrupt stack. For nested interrupts, no stack-switching is performed, because the interrupt is already set.
On the ARM, the address of routine is stored in a function pointer to be called by the stub installed on the IRQ exception vector following an asynchronous exception. This routine is responsible for determining the interrupt source and despatching the correct handler for that source.
Before calling the routine, the interrupt stub switches to SVC mode, changes to a separate interrupt stack and saves necessary registers. In the case of a nested interrupt, no SVC stack switch occurs.
OK, always.
excArchLib, excConnect( ), excVecSet( )
excCrtConnect( ) - connect a C routine to a critical exception vector (PowerPC 403)
STATUS excCrtConnect ( VOIDFUNCPTR * vector, /* exception vector to attach to */ VOIDFUNCPTR routine /* routine to be called */ )
This routine connects a specified C routine to a specified critical exception vector. An exception stub is created and in placed at vector in the exception table. The address of routine is stored in the exception stub code. When an exception occurs, the processor jumps to the exception stub code, saves the registers, and call the C routines.
The routine can be any normal C code, except that it must not invoke certain operating system functions that may block or perform I/O operations.
The registers are saved to an Exception Stack Frame (ESF) which is placed on the stack of the task that has produced the exception. The ESF structure is defined in h/arch/ppc/esfPpc.h.
The only argument passed by the exception stub to the C routine is a pointer to the ESF containing the register values. The prototype of this C routine is as follows:
void excHandler (ESFPPC *);When the C routine returns, the exception stub restores the registers saved in the ESF and continues execution of the current task.
OK, always.
excArchLib, excIntConnect( ), excIntCrtConnect, excVecSet( )
excIntCrtConnect( ) - connect a C routine to a critical interrupt vector (PowerPC 403)
STATUS excIntCrtConnect ( VOIDFUNCPTR * vector, /* exception vector to attach to */ VOIDFUNCPTR routine /* routine to be called */ )
This routine connects a specified C routine to a specified asynchronous critical exception vector such as the critical external interrupt vector (0x100), or the watchdog timer vector (0x1020). An interrupt stub is created and placed at vector in the exception table. The address of routine is stored in the interrupt stub code. When the asynchronous exception occurs, the processor jumps to the interrupt stub code, saves only the requested registers, and calls the C routines.
When the C routine is invoked, interrupts are still locked. It is the C routine's responsibility to re-enable interrupts.
The routine can be any normal C routine, except that it must not invoke certain operating system functions that may block or perform I/O operations.
Before the requested registers are saved, the interrupt stub switches from the current task stack to the interrupt stack. In the case of nested interrupts, no stack switching is performed, because the interrupt stack is already set.
OK, always.
excArchLib, excConnect( ), excCrtConnect, excVecSet( )
excVecSet( ) - set a CPU exception vector (PowerPC, ARM)
void excVecSet ( FUNCPTR * vector, /* vector offset */ FUNCPTR function /* address to place in vector */ )
This routine specifies the C routine that will be called when the exception corresponding to vector occurs. This routine does not create the exception stub; it simply replaces the C routine to be called in the exception stub.
On the ARM, there is no excConnect( ) routine, unlike the PowerPC. The C routine is attached to a default stub using excVecSet( ).
N/A
excArchLib, excVecGet( ), excConnect( ), excIntConnect( )
excVecGet( ) - get a CPU exception vector (PowerPC, ARM)
FUNCPTR excVecGet ( FUNCPTR * vector /* vector offset */ )
This routine returns the address of the C routine currently connected to vector.
The address of the C routine.
excArchLib, excVecSet( )