VxWorks Reference Manual : Libraries
cacheSh7750Lib - Hitachi SH7750 cache management library
cacheSh7750LibInit( ) - initialize the SH7750 cache library
This library contains architecture-specific cache library functions for the Hitachi SH7750 architecture. There is a 8-Kbyte instruction cache and 16-Kbyte operand cache that operates in write-through or write-back (copyback) mode. The 16-Kbyte operand cache can be divided into 8-Kbyte cache and 8-Kbyte memory. Cache line size is fixed at 32 bytes, and the cache address array holds physical addresses as cache tags. Cache entries may be "flushed" by accesses to the address array in privileged mode. There is a write-back buffer which can hold one line of cache entry, and the completion of write-back cycle is assured by accessing to any cache through region.
For general information about caching, see the manual entry for cacheLib.
cacheLib.h
cacheSh7750LibInit( ) - initialize the SH7750 cache library
STATUS cacheSh7750LibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )
This routine initializes the cache library for the Hitachi SH7750 processor. It initializes the function pointers and configures the caches to the specified cache modes. Modes should be set before caching is enabled. If two complementary flags are set (enable/disable), no action is taken for any of the input flags.
The following caching modes are available for the SH7750 processor:
The CACHE_DMA_BYPASS_Px modes allow to allocate "cache-safe" buffers without MMU. If none of CACHE_DMA_BYPASS_Px modes is specified, cacheDmaMalloc( ) returns a cache-safe buffer on logical space, which is created by the MMU. If CACHE_DMA_BYPASS_P0 is selected, cacheDmaMalloc( ) returns a cache-safe buffer on P2 space, and cacheDmaFree( ) releases the buffer to P0 space. Namely, if the system memory partition is located on P0, cache-safe buffers can be allocated and freed without MMU, by selecting CACHE_DMA_BYPASS_P0.
SH7750: CACHE_WRITETHROUGH CACHE_COPYBACK (copy-back cache for P0/P3, data cache only) CACHE_COPYBACK_P1 (copy-back cache for P1, data cache only) CACHE_RAM_MODE (use half of cache as RAM, data cache only) CACHE_A25_INDEX (use A25 as MSB of cache index) CACHE_DMA_BYPASS_P0 (allocate DMA buffer to P2, free it to P0) CACHE_DMA_BYPASS_P1 (allocate DMA buffer to P2, free it to P1) CACHE_DMA_BYPASS_P3 (allocate DMA buffer to P2, free it to P3)
OK, or ERROR if specified cache mode is invalid.