Thanks to Stan Paddock, who suggested a smaller and less intrusive change that will be nearly as tight a fix, we have a better modification than my earlier design. I would recommend that most people apply this fix rather than the daughter card method I originally developed. The most challenging part of the modification is breaking a trace connecting pins 2 and 13 of chip D-8. The trace runs underneath the chip on the same side of the PCB and I couldn't find a place to slip anything underneath to sever it. Instead, I cut pin 13 right at the PCB, bent the pin up to ensure an open circuit, then tack soldered a wire from the output of the daughter card. The other end of the short wire tacked to pin 13 of chip D-8 is soldered to ground. There are metal rails (bus-bars) that run above and below each row of chips on the card. Solder to the rail that is connected to pin 7 of chip D-8. As you can see, it is a very simple fix to the design but requires a bit of hand and soldering skill to implement due to the need to manipulate the Control Card board and chip, including safely tacking a wire onto a pin. This fix (and my prior one) causes a very slight weakening the Read Check error logic. At the time of column 0 (just to the left of the first data column) and column 81 time (just to the right of the last data column), the logic tests for any of the twelve rows having a hole (light shining through). This modification forces row 12 to be considered dark, regardless of whether there is a hole there or not. Therefore, the weakening is only for the sporadic case where the card is slipping going through the reader enough to cause the column count to be out of sync with the actual card. The error logic only triggers if the columns near the left side (e.g. 1, 2, . . .) and the columns on the right side (e.g. 80, 79 . . . ) have a hole in them. Cards with blanks on these columns will not trigger a Read Check even though the card is out of sync. If there is a hole in any row other than 12, an out of sync card will receive a Read Check. The only case where this modification blocks such a read check is if the column has only a 12 punch and nothing else in it. This affects only the percentage of cards that have a sync error and only for the percentage of all those cards that have a 12 punch ONLY in the column that will be under the photocells when the error check is made. Pretty slim odds. My original design will allow a 12 punch in the left side columns (e.g. 1) to trigger a read check if the card is out of sync, whereas this design will not, but the difference between the two designs is vanishingly small in terms of risks a card will be read without an error that would have occurred on an unmodified reader. This new mod is cleaner and thus recommended. Carl The Documation has a design flaw. Card stock can have a diagonal cutaway on the upper left or the upper right side. The diagonal cut does not extend into the area for columns 1 through 80, therefore it shouldn't cause a problem on any reader. It does, however on these machines. Let me first sketch out how the machine works (as far as reading, I won't bother with picking cards or stacking). An emitter hooked to one of the pulleys inside the machine produces pulses tied to the speed of the drive train. After a card is picked and begins to travel into the machine, the logic is waiting for any one of the 12 row photocells to go dark. It does this with a wired OR circuit labeled ONE DARK. That occurrence indicates that the leading edge of the card has arrived. Besides turning off a watchdog timer that otherwise will drive another attempt to pick (for a misfeed), it starts a column counter running. At count 1, it begins emitting the Index Marker pulses that tells the user to sample the output of the 12 row signals. For each successive column up to 80, the count triggers another index marker as the card should have its next column directly over the photocell array. IM pulses are stopped after column 80. One failure mode for the reader is that something drags on the card so that the physical card has not been in sync with the presumed card columns. For example, if there is card damage or if something in the stacker station is partly jammed and holding back our card that is being read. It is also possible but much less likely that a card moves forward faster than anticipating, so that live data columns are still unread but the counter thinks it already passed 80. The error checks for this occur at column times 81 and 84 - moving the same distance past column 80 as it moves between columns in the midst of the card. At column 84, the card should have moved completely past the photocell array, thus the error check at this time is to again sample ONE DARK. If any photocell is dark, there is part of the card blocking it which triggers an error. Now, we come to the error check that causes grief for right hand cut cards. At column 81 time, the machine samples another wired OR circuit labeled ONE LIGHT, which will be on unless all 12 rows are dark. They should all be blocked as this is the unpunched right hand side of the card. If there are any holes detected, ONE LIGHT is on and this indicates that our count of columns is wrong, we are actually over some column 80 or less. This triggers a Read Check error. It turns out that with a right hand cut card, enough light spills over the cut at the topmost part to cause the row 12 photocell to switch to 'light detected', a hole, rather than its dark state. Since it appears the card has a 12 punch over past the end of the 80 real columns, the Read Check circuit is triggered. The solution is to make row 12 appear dark at column 81 time. The only time that we have weakened the read checking operation is when a card has a last column with only a 12 punch and the card has dragged so that the last column is under the photocells when the timing believes we are at column 81. Any other holes at time 81 will rightfully trigger the error. If the card is further out of sync, it will fail the column 84 check anyway. Further, this read check will NOT detect cards that are dragged but that have spaces in their final columns. It is not definitive anyway. The wired OR that produces the inverse ONE LIGHT signal is driven by 12 open collector inverters whose input is the logical state of the 12 rows. If any rows have a 1, meaning light detected, the wired OR is pulled to ground and makes the condition ONE LIGHT true. I inserted a gate between the row 12 signal and the input to the inverter that handles row 12 for this wired OR. My gate, a NOR, takes two inputs. The timing circuits produce a pulse at column 81 time which triggers the check for ONE LIGHT; that signal is labeled 81CR. The other signal is the inverse of the row 12 state. This makes the inverter it drives pull down the wired OR only when both conditions are 0 - it is not column 81 and there is a hole detected. Any other check for ONE LIGHT will work properly, but I block the contribution of row 12 during the timing check that causes the spurious read check with right hand cut cards. Besides adding in the NOR gate, it is necessary to cut the input to the row 12 inverter feeding the ONE LIGHT wired OR, then tack on the wire from our new gate. In addition, the signal 81CR is not delivered to the Control Card where we are making this change, but it is presence on the sockets that the card plugs into. I tack a wire onto the proper gold finger to capture the 81CR signal for use with my daughter card and its NOR gate. I have run several thousand cards through with right hand cuts, extracting all the data properly but incurring no false read checks. The only time it gets a read check is when there is a hole in any of the other 11 rows at column 81, or when it fails to fully clear the photocells by column 84 time. Problem solved. Carl