LOW POWER SERIAL INPUT PLL SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1502, utilizing BI-CMOS technology, is a single chip serial input PLL
synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two
modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control
signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), 1-bit switch counter, phase
comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and
binary 11-bit programmable counter) and analog switch to speed up lock up
time.
It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ. realized through the use of Fujitsu Advanced Process Technology.
FEATURES
ABSOLUTE MAXIMUM RATINGS (See NOTE)
NOTE: Permanent device damage may occur if the above Absolute Maximum RatIngs are
exceeded.Functional operation should be restricted to the condItions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
PIN DESCRIPTION
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW=H : 64
SW=L :128
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown on following page.
7-BIT SWALLOW COUNTER DIVIDE RATIO
NOTE: Divide ratio: 0 to 127
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
PULSE SWALLOW FUNCTION
fvco = [(PxN)+A] x fosc P R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (03A3127, A<N)
fOSC: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
P: Preset modulus of external dual modulus prescaler (64 or 128)
NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider.
On rising edge of clock shifts one bit of data in the shift register.
PHASE CHARACTERISTICS
FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level (Do), phase comparator output level (jR, jP) are reversed depending upon FC pin input level. Also, monitor pin (fOUT) output level of phase comparator is controlled by FC pin input level. The relation between outputs (DO, jR, jP) and FC input level are shown below.
Note: Z = (High impedance)
VCO CHARACTERISTICS
Depending upon VCO characteristics,
FC pin should be set accordingly:
- When VCO characteristics are like1,
FC should be set High or open circuit;
- When VCO characteristics are like 2,
FC should be set Low.
NOTES: Phase difference detection range: -2p to +2p
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be connected to BlSW pin. When the analog switch is OFF, BlSW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode): Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
(Vcc=4.5 to 5.5V, TA=-40 to +85oC, unless otherwise noted.)
NOTE: 1: f in = 1.1GHz, OSClN=12MHz, Vcc=5V. Inputs are grounded and outputs are open.
2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
TYPICAL CHARACTERISTICS CURVES
INPUT SENSITIVITY
CHARACTERISTICS
INPUT IMPEDANCE
CHARACTERISTICS
TYPICAL APPLICATION
EXAMPLE
PACKAGE
DIMENSIONS
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{ 1990 FUJITSU LIMITED JV0123-90YA3
Printed in Japan