BLOCK DIAGRAM
PIN DESCRIPTION
FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fVCO = [(P x N) + A] x fOSC P R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 3 A 3 127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (6 to 16,383)
P : Preset divide ratio of modules prescaler (64 or 128)
Serial data input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the 17-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is entered via the Data pin.
One bit of data is shifted into the internal shift register on the rising edge of the clock. When the load enable pin is high, stored data is
latched according to the control data as follows:
(a) Programmable reference divider ratio
The programmable reference divider consists of a 18-bit shift register, a 17-bit latch and a 14-bit reference counter. The serial
18-bit data format is shown below:
(b) Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, a 18-bit latch, a 7-bit swallow counter, and a 11-bit programmable
counter. The serial 19-bit data format is shown below:
Serial data input timing
Power saving mode (Intermittent operation control circuit)
Setting PS bit to Low, MB1517A enters into power saving mode resultatly current sonsumption can be limited to 100mA (typ.).
Setting PS bit to High, power saving mode is released so that the device works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from power saving mode. The power
consumption can be reduced by the intermittent operation that powering down or waking up parts of the PLL circuitry. If a PLL is
powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation
between reference frequency (fR) and comparison frequency (fp) and may in the worst case take longer time for lock up of the
loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power
up, thus keeping the loop locked.
Relation between the FC input and phase characteristics
The FC pin changes the phase characteristics of the phase comparator. Both the internal charge pump output level (DO) and the phase comparator output (FR, FP) are reversed depending on the FC pin input level. Also, the monitor pin (fOUT) output is controlled by the FC pin. The relationship between the FC input level and each of DO, FR, and FP is shown below:
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
Phase comparator output waveforms
RECOMMENDED OPERATING CONDITIONS
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
- Store and transport devices in conductive containers.
- Use properly grounded workstations, tools, and equipment.
- Turn off power before inserting or removing this device into or from a socket.
- Protect leads with conductive sheet, when transporting a board mounted device.
ELECTRICAL CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
TEST CIRCUIT
(for Measuring Input Sensitivity fin/OSCin)
TYPICAL CHARACTERISTIC CURVES
TYPICAL CHARACTERISTIC CURVES (Continued)
TYPICAL APPLICATION EXAMPLE
REFERENCE INFORMATION
ORDERING INFORMATION
PACKAGE DIMENSION