Table 1. Pin Description
Table 1. Pin Description (Continued)
Table 1. Pin Description (Continued)
BLOCK DESCRIPTION
1. INTERNAL PROCESSOR (Sequencer)
Performs sequence control between the various bus phases.
2. TIMER
Manages the SCSI time standards.
Also, conducts the following time management.
w Time until the
or
signal is asserted for asynchronous transfer data
w Time until selection or reselection is retried
w
and
timeout time during transfers:
Asynchronous transfer case
Target: After the
is asserted, the time until the initiator asserts the
Initiator: After the
is asserted, the time until the target negates the
Synchronous transfer case
Target: After the
is sent, the time until an
signal which makes the offset 0 is received from the initiator
w SPC Timeout
Manages the SPC timeout indicating the SPC busy time longer than the specified time.
3. PHASE CONTROLLER
Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command, status, and message in/out.
4. TRANSFER CONTROLLER
Controls the information (data, command, status, message) transfer phases executed by SCSI.
The following two types of transfer phases are used.
Asynchronous transfer: Controls interlock (response confirmation format) between the
and
signals.
Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phases.
The following two modes exist for the data phase.
Program transfer: Uses data register (address 00/01) via the MPU interface.
DMA transfer: Uses DREQ and
signals via the DMA interface.
The transfer parameter setting values for synchronous transfers (Transfer Mode, transfer speed, transfer offset) can be stored by individual ID number and are automatically established when the data phase is initiated.
The number of transfer bytes is defined as block length y number of blocks.
5. REGISTER
The main registers are listed.
w Command register
Command is specified by an 8-bit code.
Specifies the program head address assigned to the user program memory for user program applications.
w Chip status register
Shows the chip's operating state, nexus counterpart ID, and data register state.
w SCSI bus status register
Shows the SCSI controller signal state.
w Interrupt status register
Shows 8-bit code.
w Command step register
Shows an 8-bit step code indicating the command execution state.
Error analysis can be performed by referring to the information in this register and the interrupt status register.
w Group 6/7 command length setting register
Sets the group 6/7 command length which is undefined by the SCSI standard.
By setting the command length in this register, the SPC can determine the command length.
6. RECEIVE-MCS BUFFER
A receive only, 32-byte data buffer which stores data received via SCSI (message, command, status)
M: Message C: Command S: Status
7. SEND-MCS BUFFER
A send only, 32-byte data buffer which stores data sent via SCSI (message, command, status).
8. COMMAND USER PROGRAM MEMORY
Program memory used for establishing programmable commands (256 bytes).
9. DATA REGISTER
FIFO-type data register which stores data from SCSI executed data phases (32 bytes).
Table 2. Phase Status
Note : Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
MPU Interface (80 series)
w Register write timing
w Register read timing
w Register write timing (for external access)
w Register read timing (for external access)
MPU Interface (68 series)
w Register write timing
w Register read timing
w Register write timing (for external access)
w Register read timing (for external access)
DMA Interface
The DMA access timing described in this section is not applicable in the following cases.
w During SCSI input, when the data buffer is EMPTY or when one byte is stored
w During SCSI output, when the data buffer is FULL or when 31 bytes are stored
w When a parity error is detected (target)
wWhen an error which interrupts the transfer occurs at the SCSI interface
[80 Series Handshake Mode]
w Read timing
[68 Series Handshake Mode]
w Write timing
w Read timing
[Burst Mode (80 series/68 series common)]
w Data register access cycle time (8 bit)
w Data register access cycle time (16 bit)
[80 Series Burst Mode]
w Write timing
w Read timing
[68 Series Burst Mode]
w Write timing
w Read timing
SCSI Interface (as Initiator)
[Asynchronous transfer Mode]
w Input timing (target " initiator)
*1 The REQ H " ACK L time (tRQAK2) is compared with (tRQAKH + tAKRQL + tRQAK1) and the longer value is chosen.
Note: The input timing definition is not applied in the following cases.
* When the data register is FULL in the data phase
* When the final byte is being transferred
w Output timing (initiator " target)
* S value is based on the asynchronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
[Synchronous transfer Mode]
w
/
signal period
*1 A and N values are based on the transfer period register (address 0Dh) setting.
w Input timing (target " initiator)
w Output timing (initiator " target)
*2 A and N values are based on the transfer period register (address 0Dh) setting.
SCSI Interface (as target)
[Asynchronous transfer Mode]
w Input timing (initiator " target)
*1 The
L "
L time (tAKRQ2) is compared with (tAKRQH +
tRQAKH + tAKRQ1) and the longer value is chosen.
Note: The input timing definition is not applied in the following cases.
* When the data register is FULL in the data phase
w Output timing (target " initiator)
*2 S value is based on the asynchronous set up time setting register (address 17h).
Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
[Synchronous transfer Mode]
w
/
signal period
*2 A and N values are based on the transfer period register (address 0Dh) setting. See (8) for more on setting values.
w Input timing (target " initiator)
w Output timing (initiator " target)
*2 A and N values are based on the transfer period register (address 0Dh) setting.
(8) A/N/S Values in SCSI Interface Timing
w Transfer period register (address 07h) and A/N values
The A and N values set in the register represent the assert period and the negate period respectively (unit is clock cycles).
For AC characteristics, A/N use numerals.
w Asynchronous set up time setting register (address 17h) setting values and S value
The S (set up time) value established in the set up time setting register during asynchronous data transfers indicates the time from setting data in the
data bus until the
/
signals are asserted.
For AC characteristics, S uses numerals.
LIST OF REGISTERS
1. Basic Control Registers (for write)
2. Basic Control Registers (for read)
Note: y indicates data undefined (0 or 1).
3. Initial Setting Window (for write/read)
4. Mcs Buffer Window
5. User Program Memory Window
LIST OF COMMANDS
SPC commands can be specified by the command register or the user program memory and are divided into the following main groups.
w Sequential commands
Commands which perform a consecutive (including phase transition) sequence operation. Can only be specified by the command register (1 byte).
w Discrete commands
Commands which perform operations from disassembled sequential commands. Can be specified by the command register (1 byte command) or the user program memory (1/2 byte command).
w Special commands
Can only be specified by the user program memory (1/2 byte command).
1. Initiator Commands
(1) Sequential commands
(2) Discrete commands
2. Target Commands
(1) Sequential commands
(2) Discrete commands
3. Common Commands
4. Programmable Commands
The user program is stored in the user program memory and begins operation when the user program head address is written in the command register.
Programmable commands are either discrete or special commands and have a command length of one (1) or two (2) bytes.
w Command Field Assign
SYSTEM CONFIGURATION EXAMPLE
1. 80 Series, Separate Bus Type
2. 80 Series, Shared Bus Type
3. 68 Series, Separate Bus Type
4. 68 Series, Shared Bus Type
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