The MB1515 is a serial input PLL (Phase-Locked Loop) frequency synthesizer with
a built-in prescaler allowing for a pulse swallow system in the two modulus 2.5 GHz
band. It is suitable for BS and TV tuners and CATV systems.
The synthesizer is powered by 5 V (typical). Using the latest proprietary process, current consumption has been reduced to ICC = 16 mA (typical).
Features
S Supply voltage: VCC = 5 V
S High-speed operation capability: fin = 2.5 GHz (Vin = - 4 dBm)
S Low current consumption: ICC = 16 mA (typical)
S Broad operating temperature range: Ta = - 405C to +855C
S Integrated Functions
24-bit shift register
24-bit latch
Reference divider
Binary 2-bit programmable reference counter (Divide ratios: 256, 512,
1024, and 2048)
Comparison Divider
Binary 5-bit swallow counter (Divide ratios: 0 to 31)
Binary 12-bit bit programmable counter (Divide ratios: 32 to 4095)
Phase comparator with phase conversion feature
Two modulus prescaler for 2.5 GHz band (Divide ratios: 256/272 and 512/528)
4-bit band switching signals
Control signal generator
Crystal oscillator
Charge pump
MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
NOTES:
1. To prevent damage caused by static electricity, an antistatic element is added and antistatic enhancement is also built into the circuit. However, the following handling cautions must be observed:
PIN DESCRIPTION
BLOCK DIAGRAM
ELECTRICAL CHARACTERISTICS
Functional Descriptions
1. Formula for calculation of divide ratio
Set divider's divide ratio according to the following formula:
fVCO = [(P y N) + (16 y A)] y fOSC P R
where
fVCO : Externally connected VCO output frequency
P : Prescaler divide ratio (256 or 512)
N : Binary 12-bit programmable counter setting (32 to 4095)
A : Binary 5-bit swallow counter setting (0 to 31)
fOSC : Reference oscillation frequency
R : Reference counter setting (256, 512, 1024, 2048)
2. Serial data input procedure
Serial data is input from three inputs, Data pin, Clock pin and LE pin, allowing for control of the 4-bit band switch setting, the 3-bit reference divider and the 17-bit comparison divider respectively. The data is sequentially fetched into the internal shift register at the rising edge of the clock and transferred to the latch when load enable is at the "H" level.
The 24-bit shift register is configured as follows:
S Band switch setting (BC1 to BC4)
When data set in the band bits is at "H," output is turned ON. When data is at "L," output is turned OFF.
S Prescaler divide ratio (SW)
Divided by 256/272 when data set in the SW bit is at "H." Divided by 512/528 when data is at "L."
S Divide ratios for 5-bit swallow counter (A1 to A5)
S Reference counter divide ratios (R1 and R2)
S Divide ratios for 12-bit programmable counter (N1 to N12)
3. Serial data input timings
When designing the synthesizer, control the FC pin according to the VCO polarity.
*: Fetches data at the rising edge of the clock.
*: Fetches data when LE is at "H" level.
4. FC pin input in relation to phase characteristics
The FC pin switches the phase of the phase comparator. Phase characteristics (charge pump output) are inverted by controlling this pin. Output from the phase comparator input monitor pin (fout) is also controlled by this FC pin. The relation of FC pin input with Do and fout is as follows:
Z: high impedance
When designing the synthesizer, control the FC pin according to the VCO polarity.
Phase Comparator Output Waveforms
Notes:
1. The phase error is detected in a range of - 2 p to +2 p.
2. Output of a "glitch" varies slightly with charge pump characteristics. This "glitch" is output to eliminate an dead band.
Example Measurement Circuit (Prescaler input sensitivity)
Equivalent Circuit Diagram
Example Application
C1, C2: Determined by the crystal oscillator
FC: with pull up resistor
Ordering Information
external dimensions
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
This document contains information on a new product. Specification and information herein are subject to change without notice.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.
FUJITSU LIMITED
For further information please contact:
WFUJITSU LIMITED 1994 DS04-21317-2E