PIN DESCRIPTIONS



PIN DESCRIPTIONS



FUNCTIONAL DESCRIPTIONS

1. Circuit Description

1.1 Intermittent Operation

The intermittent operation of the MB87091 refers to the process of activating and deactivating its internal circuit as necessary thus saving power dissipation otherwise consumed by the circuit. If the circuit is simply restarted from the stand by state, however, the phase relationship between the reference frequency (fr) and the programmable frequency (fp), which are the input to the phase comparator, is not stable even when they are of the same value. This may cause the phase comparator to generate an excessively large error signal, resulting in an out-of-synch lock frequency.

To preclude the occurrence of this problem, the MB87091 has an intermittent mode control circuit which forces the frequencies into phase synchronization with each other when the MB87091 is reactivated, thus minimizing the error signal and resultant lock frequency fluctuations. The intermittent mode control circuit is controlled by the PS pin. Setting pin PS high provides the normal operation mode and setting the pin low provides the standby mode and places the MB87091 into the stand by state. The MB87091 behavior in the active and stand by modes is summarized below.

1.2 Programmable Divider

The fVCO input through fin pin is divided by the programmable divider and then output to the phase comparator as fp. It consists of a dual modulus prescaler, a 6-bit binary swallow counter, a 12-bit binary programmable counter, and a controller which controls the divide ratio of the prescaler.

Divide ratio range:
w Prescaler: M = 64, M+1 = 65
w Swallow counter: A = 0 to 63
w Programmable counter: N = 5 to 4095

The MB87091 uses the pulse swallow method; consequently, the divide ratios of the swallow and programmable counters must satisfy the relationship N > A.

The total divide ratio of the programmable divider is calculated as follows:
Total divide ratio = (M+1)xA+Mx(N-A) = MxN+A = 64xN+A

When N is set within 5 3 N 3 63, the possible divide ratio A of the swallow counter can take values 0 3 A 3 N-1 because N must be greater than A. For example, 0 3 A 3 19 is allowed when N = 20 but 20 3 A 3 63 is not allowed in that case. Consequently, N . 64 must be satisfied for the total divisor to be set within 0 3 A 3 63.

The fp and fin have the following relationship:
fp = fin P (64 y N + A)

1.3 Programmable Reference divider

The programmable reference divider divides the reference oscillation frequency (fOSC) from the crystal oscillator connected between OSCIN and OSCOUT pins or from the external oscillator input taken in directly through OSCIN pin, then, sends the resultant fr to the phase comparator. It consists of a 14-bit binary programmable reference counter. When the output from the external oscillator is to be input directly to OSCIN, pin the connection must be AC coupled and OSCOUT pin is left open. Also, to prevent OSCOUT from malfunctioning, its traces on the printed circuit board must be kept minimal or eliminated entirely; whenever possible, it must be free of any form of load.

The following divisor is used:
w Programmable reference counter: N = 5 to 16383
The fr and fOSC have the following relationship:
w fr = fOSC P R

1.4 Phase Comparator

The phase comparator detects the phase difference between the outputs fr and fp from the dividers and generates an error signal that is proportional to the phase difference. The outputs from the phase comparator include 1) DO which takes on one of the three states, namely, "L" (low), "H" (high), and "Z" (high impedance), and is sent to the LPF, 2) fR, 3) fP, and 4) LD which indicates the PLL lock or unlock state.

1.4.1 Phase Comparator

The phase comparator detects the phase difference between fr and fp and generates an error signal that is proportional to the phase difference. The roles of the fr and fp supplied to the phase comparator may be reversed by switching the logical input level on FC pin. This inverts the logical level on the DO output. The logical level on DO output may be selected according to the characteristics of the external LPF and the VCO. (Refer to Table 1.)

Table 1 Phase Comparator Inputs/Output Relationships



1.4.2 Charge Pump

The charge pump is available in two forms: internal and external.
w Internal constant-current charge pump output (DO)
w External charge pump outputs (fR, fP)

The output current at DO pin from the internal constant-current charge pump is controlled by varying the external resistance (RRC) connected between RC and GND as shown in Figure 1.



Figure 1 Constant-current Charge Pump

1.4.3 Phase Comparator Input/Output Waveforms

The phase comparator outputs logic levels summarized in Table 1, according to the phase difference between fr and fp phase differences. Note that fP is an Nch open drain output. The pulse width of the phase comparator outputs are identical and equal to the phase difference between fr and fp as shown in Figure 2.



1.4.4 Lock Detector

The lock detector detects the lock and unlock states of the PLL. The lock detector outputs "H" when the PLL enters the lock state and outputs "L" when the PLL enters the unlock state as shown in Figure 3. When PS = "L", the lock detector outputs "H" compulsorily.



2. Setting the Divide Ratio

2.1 Serial Data Format

The format of the serial data is shown in Figure 4. The serial data is composed of a control bit and divide ratio setting data. The control bit selects the programmable divider or programmable reference divider.
In case of the programmable divider, serial data consists of 18 bits (6 bits for the swallow counter and 12 bits for the programmable counter) and 1 control bit as shown in Figure 4.1. In case of the programmable reference divider, the serial data consists of 14 divisor bits and 1 control bit as shown in Figure 4.2.
The control bit is set to 0 to identify the serial data for the programmable divider and to 1 to select the serial data for the programmable reference divider.



2.2 The Flow of Serial Data

Serial data is received via data pin in synchronization with the Clock input and loaded into shift register which contains the divide ratio setting data and into the control register which contains the control bit. The logical product (through the AND gate in Figure 5) of LE and the control register output (i.e., control bit) is fed to the Enable input of the latches. Accordingly, when LE is set high, the latch for the divider identified by the control bit is enabled and the divide ratio data from the shift register is loaded into the selected counter(s).



2.3 Setting the Divide Ratio for the Programmable Divider

Columns A0 to A5 of Table 2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of Table 2.2 represent the divide ratio of the programmable counter. The control bit is set to 0.

Table 2 Divide Ratio for the Divider



2.4 Setting the Divide Ratio for the Programmable Reference Divider

Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is set to 1.

Table 3 Divide Ratio for the Reference Divider



2.5 Serial Data Input Timing

The MB87091 uses 19 bits of serial data for the programmable divider and 15 bits for the programmable reference divider. When more bits of serial data than defined for the target divider are received, only the last valid serial data bits are effective.
To set the divide ratio for the MB87091 dividers, it is necessary to supply the Data, Clock, and LE signals at the timing shown in Figure 6.

t1 (.1 ms) : Data setup time t2 (.1 ms): Data hold time t3 (.1 ms): Clock pulse width
t4 (.1 ms) : LE setup time to the fall edge of last clock t5 (.1 ms): LE pulse width



Since the divide ratios are unpredictable when the MB87091 is turned on, it is necessary to initialize the divide ratio for both dividers at power-on time. As shown in Figure 7, after setting the divide ratio for one divider (e.g., programmable reference divider), set LE to the "H" level before setting the divide ratio for the other divider (e.g., programmable divider). To change the divide ratio of one divider after initialization, input the serial data only for that divider (the divide ratio for the other divider is preserved).



RECOMMENDED OPERATING CONDITIONS



ELECTRICAL CHARACTERISTICS



TYPICAL APPLICATION EXAMPLE



PACKAGE DIMENSIONS



PACKAGE DIMENSIONS (CONTINUED)



PACKAGE DIMENSIONS (CONTINUED)