

PIN DESCRIPTION

FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored
data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.

14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO

PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown following page.

7-BIT SWALLOW COUNTER DIVIDE RATIO

11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO

PULSE SWALLOW FUNCTION
fVCO= [(PxN)+A] xfOSCPR
fVCO:Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (03A3127, A<N)
fOSC:Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 14-bit programmable reference counter (8 to16383)
P: Preset modulus of external dual modulus prescaler (64 or 128)

PHASE CHARACTERISTICS


ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
LE=L (Normal operating mode) : Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

TEST CIRCUIT

TYPICAL APPLICATION EXAMPLE

PACKAGE DIMENSIONS

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