The MB86951 is a 10 Mbit/sec Manchester
encoder/decoder that is designed to meet the
requirements for Ethernet local area networks. This
device, when used with companion chips such as
Fujitsu's MB86950 EtherStar] Controller and either the
MBL8392A Coaxial Transceiver or the MB86962
Twisted Pair Transceiver (see Figure 1), forms a complete
chip set that meets the requirements of the
ISO/ANSI/IEEE 8802-3 international standard for
Ethernet, Thin Net, and 10BASE-T networks.
The encoder/decoder interfaces with the network controller on the system side and with the transceiver on the network side. It contains a receiver with phase locked loop, a driver, a collision signaling detector, and an oscillator.
During transmit operation, the MB86951 receives NRZ (non-return-to-zero) data from the controller and converts the serial binary data stream into a Manchester encoded stream which is transmitted out on a balanced differential pair to the transceiver. During receive operation it converts Manchester encoded data on a balanced differential pair from the transceiver into NRZ data and forwards it to the controller, together with a 10 MHz synchronous receive data clock. A phase locked loop is used for clock recovery to allow a worst case jitter of +20 ns.
The MB86951 is fabricated using Fujitsu's high speed, low power, CMOS technology and is supplied in 24-pin plastic DIP and small outline (SOP) packages.
PIN CONFIGURATION
BLOCK DIAGRAM
The block diagram highlights the major functional blocks
of the MB86951: oscillator, data encoder, data decoder,
collision signal detector, and loopback control. Figure 1
illustrates a typical interface for the device when driving
an AUI (transceiver) cable on the network side and
connected to Fujitsu's MB86950 EtherStar controller on
the system side.
OSCILLATOR
The IEEE 802.3 standard specifies a clock rate of 10 Mbits/sec. This is obtained from a 20 MHz clock generated by the oscillator, which operates from an external crystal reference connected between pins X1 and X2 of the MB86951. Crystal capacitance as specified by the manufacturer should be connected from X1 and X2 to ground, considering any stray capacitance which can vary the crystal's frequency. If an external 20 MHz clock is available, it may be applied to X1 with X2 left unconnected.
The 20 MHz oscillator output is provided on CKOUT for external use. It is also divided by two to produce the required 10 MHz clock, which is used internally and furnished on TCKN(-TCKN) for use by the network controller. The 20 MHz clock also serves as a reference for an internal phase locked loop used for clock and data recovery in the decoder section.
DATA ENCODER
Manchester encoding is used for the transmission of data from the MB86951. Manchester encoding is a binary signaling mechanism that combines data and clock into bit symbols. Each bit symbol is split into two halves, with the signal polarity of the second half being the inverse of that of the first half. A transition always occurs in the middle of each bit symbol, with logic `0' and `1' encoded as 1-to-0 and 0-to-1 transitions respectively. See Figure 2. In the case of the MB86951, the controller asserts
transmit enable (TEN) to indicate that the outgoing packet on TXD is valid data. This NRZ serial data input must be supplied synchronously with the TCKN(-TCKN) clock as required by the setting of MODE. If MODE=1, TXD is valid during the rising edge of TCKN(-TCKN); if MODE=0, TXD is valid during the falling edge. The Manchester-encoded signals are output through a differential driver to the transceiver through TXDATA+ and TXDATA-, and are present as long as the TEN pin remains affirmed.
The differential driver is capable of driving a 50 meter segment of 78W interface cable, as specified in the ISO/ANSI/IEEE 8802-3 standard. 270W resistors are required externally to pull down TXDATA+ and TXDATA-. See Figure 3.
DATA DECODER
The data decoder section performs three functions on the data received at the differential receive inputs (RXDATA+ and RXDATA-) from the transceiver: carrier detection, clock recovery, and Manchester data decoding.
Clock recovery is accomplished by use of phase locked
loop circuitry which uses the crystal oscillator as a
reference. Use of a PLL provides the most reliable and
robust clock recovery. It allows signal acquisition to be
accomplished within six bit times from first detection of
the signal, and permits stable operation with input signal
jitter of up to +20 ns. Carrier detection is indicated to the
controller by affirmation of the XCD output, which
occurs shortly after a signal appears at the differential
inputs.
The recovered clock is supplied to the controller on RCKN(-RCKN), and is also used to convert the Manchester encoded data to NRZ format, which is then output on RXD. The phase relationship between RCKN(-RCKN) and RXD is controlled by the MODE input. Transitions in the state of RXD are synchronous with the rising edge of RCKN(-RCKN) if MODE = 0, and synchronous with the falling edge of RCKN(-RCKN) if MODE = 1. RCKN(-RCKN) is a free running 10 MHz clock when no receive signal is present.
The RXDATA+ and RXDATA- differential inputs must
be terminated with two 39W resistors in series with a 0.1
mF bypass capacitor at their junction, as illustrated in
Figure 2.
COLLISION SIGNALING DETECTOR
As collisions are detected on the network media, the transceiver generates a 10 MHz signal on the COL+ and COL- differential inputs to the MB86951. This signal is detected by the MB86951, converted to a logic-level signal appropriate for the controller and output on -XCOL(XCOL). If MODE = 0, -XCOL(XCOL) is normally low and changes to a high state during collision detection. If MODE = 1, -XCOL(XCOL) is normally high and changes to a 10 MHz pulse stream during collision detection.
The COL+ and COL- differential inputs require 78W W termination like that for the RXDATA+ and RXDATA- inputs. See Figure 2.
LOOPBACK
The loopback control input (LBC) causes transmitted data from the controller to be routed through the internal circuits of the MB86951 and back to the received data output to test for proper system operation. While LBC is affirmed, the encoded transmit data is supplied to the data decoder instead of the receive data from the RXDATA+ and RXDATA- inputs. Also, the differential transmit drivers and the collision signal detector are disabled. Note that changes in LBC while data is being received may cause errors in the received data output.
MODE CONTROL
The MODE input selects one of two modes of operation for the MB86951. The setting of this input changes the phase relationship between certain clocks and signals, and the format of the -XCOL(XCOL) output. The three signal pins which are affected are -XCOL(XCOL), RCKN(-RCKN) and TCKN(-TCKN). MODE =1 selects the normal mode in which these signals are compatible with Fujitsu controllers such as the MB86950. When MODE = 0 the MB86951 is functionally and electrically compatible with the National DP83910 and the AMD Am7992. Polarity of the three signal pins shown in their names in parentheses corresponds to MODE = 0. See the Pin Descriptions section and the timing diagrams at the end of this data sheet for additional information.
POWER DOWN
The power down mode is selected by driving both -PWRDN (pin 20), and LBC (pin 7) low. In this mode, power consumption is reduced to 6 mA typical.