- Provides Plug and Play compatibility for ISA add-in cards
- Conforms to Plug and Play ISA Specification v1.0a
- Can be used in non Plug and Play environment
- Serial interface for resource EEPROM including support for storage and retrieval of Plug and Play data structures and user defined data.
- Support for two DMA channels and two interrupt lines
- Interrupts routed to any of 11 ISA bus interrupt channels
- Programmable interrupt input polarity
- DMA routed to any of 7 ISA bus DMA channels
- Four chip select outputs - two I/O, two memory
- Generates /IOCS16 and /MEMCS16 control signals
- Four general purpose I/O lines
- Maps memory to fixed address for FIFO string moves
- 144-pin SQFP (MB86701), 120-pin PQFP (MB86701A)
- 5 volt power supply
- Low power CMOS technology
- Provides auto-configuration of cards when installed in Plug and Play systems
- Reduces cost of customer support by reducing or totally eliminating installation-related problems
- Eliminates jumpers, switches and corresponding decoding logic
- Eliminates the need for special hardware and software related to proprietary schemes for software configuration
- Adds Plug and Play functionality to existing board designs with a minimum of re-engineering
The MB86701/701A Plug and Play ISA Controller (PPIC) is a single-chip solution offering all the hardware resources required to build ISA cards compliant with the Plug and Play ISA Specification v1.0a. An external serial EEPROM stores card resource requirements information and can also store additional user-defined data, such as an Ethernet ID or manufacturing traceability information. Configuration information provided by the Plug and Play software is stored in registers as defined in the specification. The MB86701/701A performs all I/O and memory address decoding as well as interrupt and DMA request routing. Stored configuration information is decoded to properly route interrupt and DMA requests. Users may direct card DMA to any of seven DMA channels on the ISA bus and interrupts to any of eleven interrupt channels on the ISA bus. Two separate DMA channels and two separate interrupts lines for logical devices are supported.
The PPIC also provides additional features not required by the specification that can enhance card performance and reduce cost. For example, a four-bit I/O port is provided with lines that are independently configurable as input or output. These lines allow control of functions such as media selection for a LAN card or monitoring of external events.
The following table summarizes the basic capabilities of the MB86701/701A:
A unique feature of the MB86701/701A allows the mapping of any access to a user-defined memory window into a single user-defined address on the logical device side of the chip. This is done by providing a single output composed of two of the chip select signals, while simultaneously providing combined read and write strobes. This allows driver software to use memory-reference instructions to access a fixed-address register on the card and thus improves data-transfer performance. For example, this feature can be used to move a sector of data to or from a FIFO on a SCSI card using string or block move instructions instead of a loop of I/O instructions.
The MB86701/701A is fabricated using a low-power CMOS process and is available in 120- and 144-pin quad flat packages.
PIN ASSIGNMENT - MB86701 (144-PIN SQFP)
Note:
1. Numeric suffix indicates output current capability. See DC Characteristics. (PU) indicates internal pull-up resistor, (PD) indicates internal pull-down resistor.
2. Open drain outputs.
ORDERING CODE
PIN ASSIGNMENT - MB86701A (120-PIN PQFP)
Note:
1. Numeric suffix indicates output current capability. See DC Characteristics. (PU) indicates internal pull-up resistor, (PD) indicates internal pull-down resistor.
2. Open drain outputs.
ORDERING CODE
Unless otherwise noted, a positive logic (active high) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A preceding slash, e.g., /RESET, indicates that the signal is asserted in a low state (nominally 0 volts). Whenever a signal is separated into numbered bits, e.g., ADD6, ADD5, ADD4, ADD3, ADD2, ADD1, ADD0, the family of bits may also be shown collectively, e.g., as ADD<6:0>.
ISA BUS INTERFACE SIGNALS
EEPROM BUS INTERFACE SIGNALS
DEVICE INTERFACE SIGNALS
The MB86701/701A is a generic Plug and Play device which when attached to ISA compatible controllers enables them to operate in the Plug and Play environment. In the Plug and Play environment users may plug peripheral cards such as LAN cards, graphics adapters or hard-disk controllers into their machines and system software configures each card automatically at power-up time. The need for configuration jumpers and switches on the adapter card is eliminated and installation of cards becomes more user friendly.
The MB86701/701A is based on the Plug and Play ISA Specification v1.0a and meets all ISA timing specifications as well.
The Plug and Play concept is built around the following four states: (1) Wait for Key (2) Sleep (3) Isolation and (4) Configuration. At power up, the cards begin in the Wait for Key state, awaiting the initiation key with outputs disabled. Once the initiation key is received, the Sleep state begins. The card remains in the Sleep state until it receives a Wake[CSN] command with the parameter data set to zero upon which the Isolation state is entered. After the card is isolated, it receives a unique Card Select Number (CSN). Once the CSN is written, the card moves into the Configuration state and its resources are read. All cards in a system follow the same procedure until their resource requirements are known.
Note: The following sections provide a brief overview of the Plug and Play configuration process. Please refer to the Plug and Play ISA specification for additional information. Copies of this specification are available from Fujitsu upon request. Contact your local Fujitsu sales office, representative or distributor.
Plug and Play Card Configuration Sequence
The MB86701/701A PPIC contains all the hardware resources required to allow the card to be identified and auto-configured by the Plug and Play software resident in the host system.
The auto configuration process consists of the following steps:
- All Plug and Play ISA cards are placed in the Sleep state.
- All Plug and Play ISA cards are isolated one at a time.
- As each card is isolated, assign a handle and read the card's resource data structure
- After the resource requirements and capabilities are determined for all cards, the handle is used to place the card in Configuration state and assign conflict free resources to each card.
- All Plug and Play ISA cards are activated and removed from Configuration state.
The Plug and Play software uses three 8-bit I/O ports to execute a set of commands that identify and configure devices. A sequence of data writes to one of the ports, referred to as the initiation key, is used to enable the Plug and Play logic on all cards in the system.
Because all Plug and Play cards can respond to the same I/O port addresses, an isolation mechanism is required for the Plug and Play software to address each card independently. During Isolation, an isolation protocol is used to read a unique identifier on each card to isolate one Plug and Play card at a time. Following Isolation, the Plug and Play software assigns each card a handle (CSN) which is used to address that unique Plug and Play card. The software then reads the resource data structure which describes the resources supported and those requested by functions on the card.
When all resource capabilities and demands of the cards are known, the process of resource arbitration is invoked to determine resource allocation to each ISA card. A conflict detection mechanism is invoked to insure that resources assigned are not in conflict with standard ISA cards.Then, using the previously assigned handle, each Plug and Play card is placed in the Configuration state and the card is configured with the allocated resources through the Plug and Play standard registers. If the resources requested are not reconfigurable, equivalent resources will be supported. The resource data structure will inform the arbiter that the requested resources cannot be assigned to other Plug and Play cards in the system.
The command set also supports the ability to activate or deactivate the functions on the card.
Once the configuration is completed, Plug and Play cards are removed from the Configuration state and placed in normal system operation mode. To enter the Configuration state again, the initiation key must be re-issued. This process prevents accidental erasure of the configuration information.
State Summary
The Plug and Play logic is quiescent on power up (Wait for Key state) and must be enabled by software. A predefined series of writes to the ADDRESS port places the Plug and Play logic into Sleep state. This is referred to as the initiation key. The write sequence is decoded by on-card logic, and if the proper series of I/O writes is detected, the auto-configuration ports are enabled. If the data does not match, the internal logic is reinitialized and the PPIC remains in the Wait for Key state.
On each ISA card there exists an 8-bit register called the Card Select Number (CSN) register (0x06) used to select one or more ISA cards when those cards are in certain states. The CSN mechanism allows a wide variety of devices to manage their configuration and control. The CSN register is set to 0x00 on all cards on power up. Once a card has been isolated, the CSN on that card is assigned a unique value which enables the Plug and Play software to select this card later in the configuration process, without going through the protocol again.
The four Plug and Play states (see Figure 1) are summarized as follows:
- Wait for Key - Upon power-up reset and Wait for Key commands, all cards enter this state. No commands are active in this state until the initiation key is detected on the ISA bus. It is the default state for Plug and Play cards during normal system operation. After configuration and activation, software should return all cards to this state.While in the Wait for Key state, cards do not respond to any access to their auto-configuration ports until the initiation key is detected. All ISA accesses from the Plug and Play interface to the cards are ignored.
- Sleep - Plug and Play cards wait for a Wake[CSN] command in this state. Based on the write data and the value of the CSN on each card, this command will selectively enable one or more cards to the Isolation or Configuration states. To exit this state, the value of the write data bits[7:0] of the Wake[CSN] command must match the card's CSN. If the write data for Wake[CSN] is zero, then all cards that have not been assigned a CSN will enter the Isolation state. If the write data for the Wake[CSN] command is nonzero, then the one card whose assigned CSN matches the parameter of the Wake[CSN] command will enter the Configuration state.
- Isolation - The first time the cards enter the Isolation state, it is necessary to set the READ_DATA port address using the Set RD_DATA port command. Seventy-two pairs of reads are performed to the Serial Isolation register to isolate a card. If the checksum read from the card is valid, then one card has been isolated. The isolated card remains in the Isolation state. All other cards which have failed the isolation protocol will return to the Sleep state. The isolated card is assigned a unique value called the Card Select Number (CSN) and transitions to the Configuration state. The Wake[0] command causes the card to transition back to the Sleep state and all cards with a CSN value of zero transition to the Isolation state. This entire process is repeated until all Plug and Play cards are detected.
- Configuration -In this state, the card responds to all configuration commands including reading the card's resource configuration information and programming the card's resource selections. Only one card may be in this state at a time.
Figure 1. Plug and Play Configuration Process States
Notes:
1. CSN = Card Select Number.
2. RESET_DRV causes a state transition from the current state to Wait for Key and sets all CSNs to zero. All logical devices are set to their power-up configuration values.
3. The Wait for Key command causes a state transition from the current state to Wait for Key.
Auto-Configuration Ports
Three 8-bit ports are used by the software to access the configuration space on each Plug and Play ISA card. The ports are listed in Table 1. These registers are used by the Plug and Play software to issue commands, check status, access the resource data information, and configure the Plug and Play hardware. The ports have been chosen to avoid conflicts in the installed base of ISA functions, while at the same time minimizing the number of ports needed in the ISA I/O space.
Table 1. Auto-Configuration Ports
Notes:
1. Address is 0x0259 if NEC input is asserted.
2. Address is 0x0A59 if NEC input is asserted.
The three auto-configuration ports use a 12-bit ISA address decode. The ADDRESS and WRITE_DATA ports are located at fixed addresses. The WRITE_DATA port is located at an address alias of the ADDRESS port. The READ_DATA port, which is the only readable auto-configuration port, is relocatable within the I/O range from 0x0203 to 0x03FF. The address of the READ_DATA port is assigned by the system software and is set by writing the proper value to Plug and Play control register 0x00 (Set RD_DATA Port command). The isolation protocol verifies that the location selected for the READ_DATA port is free of conflict.
The Plug and Play registers within the PPIC are accessed by writing the address of the desired register to the ADDRESS port, followed by a read of data from the READ_DATA port or a write of data to the WRITE_DATA port. A write to the ADDRESS port may be followed by any number of WRITE_DATA or READ_DATA accesses to the same register location without the need to write to the ADDRESS port before each access.
Obtaining The Device Configuration
The driver or other application software requires a mechanism to determine the configuration information in order to communicate with the card. An Application Programming Interface (API) exists to provide the required data. Called the Plug and Play Configuration Manager API, it is documented in the "Plug and Play Device Driver Developer's Guide" (Intel Publication Number 485473-001) or equivalent documentation provided by the supplier of the Plug and Play system software. Also see "Plug and Play Device Driver Interface for Microsoft Windows 3.1 and MS-DOS" (available on the Plug and Play forum on CompuServe).
The API requires only two calls to retrieve configuration:
- CM_GetVersion verifies the presence of the Configuration Manager.
- CM_GetConfig retrieves the configuration information from an indexed, system wide table. This information includes READ_DATA port address, Card Select Number (CSN) and resource allocation for each configured device.
The Configuration Manager also provides a Configuration Access (CA) support interface. Two calls associated with this interface of particular interest are:
- CA_GetVersion verifies the presence of the Configuration Access support interface.
- CA_PnPISA_Get_Resource_Data retrieves the resource data stored in the EEPROM connected to the MB86701/701A and can be used to obtain the data stored in the "Vendor Defined" resource data types.
Table 2. MB86701/701A Register Set
Note 1. See Table 11.
Note 2. See Table 12.
Note 3. See Table 13.
Note 4: Default value = (EE0x00F<0>) OR (NOT(/ACTIV)).
Operation of the PPIC is controlled by values written into registers within the device while other registers provide device status. The register set consists of a combination of Plug and Play standard registers and vendor defined registers. Table 2 is a map of the user-accessible registers implemented in the MB86701/701A. In this table, an "X" in the STD column indicates that this is a standard PnP register and is described in the Plug and Play ISA specification (Appendix A). The table also provides default values (DEF) and defines, for each Plug and Play state, the type of access available. Exceptions to the specification are detailed in Table 3. Vendor-defined registers contained in the PPIC are described in Tables 4 to 13.
As previously described, the registers are accessed for read and write operation via the ADDRESS, WRITE_DATA and READ_DATA auto-configuration ports (see Table 1). The ADDRESS and WRITE_DATA ports have defined ISA addresses. In a PnP system, the READ_PORT address is normally assigned by the PnP system software during Isolation. In that environment, the address of the READ_DATA port can be determined by using the CM_GetConfig call to the Configuration Manager as previously described. In a non-PnP system, the READ_DATA port address will have been assigned by the configuration utility used to configure the card, and can be determined as appropriate for that software.
Table 3. MB86701/701A Standard PnP Register Exceptions
Table 4. PIO Data (0x20)
Table 5. PIO Data Direction (0x21)
Table 6. EEPROM Write Enable/Write Disable (0x22)
Table 7. EEPROM Write Data Low (0x23)
Table 8. EEPROM Write Data High (0x24)
Table 9. MB86701/701A PnP State (0x25)
Table 10. EEPROM Command (0x26)
Table 11. I/O Range 0(1)
Note:
1. This internal register is not user accessible. It is automatically loaded at reset with the value stored in byte 0x010 in the EEPROM.
Table 12. I/O Range 1(1)
Note:
1. This internal register is not user accessible. It is automatically loaded at reset with the value stored in byte 0x011 in the EEPROM.
Table 13. Memory Mapped I/O Register Address(1)
Note:
1. This internal register is not user accessible. It is automatically loaded at reset with the value stored in byte 0x00E in the EEPROM. See Memory to I/O Mapping Section of data sheet.
Control Register Summary
Plug and Play cards respond to commands written to Plug and Play registers as well as certain ISA bus conditions. These commands are summarized below:
- RESET_DRV - This is the ISA bus reset signal. Upon detection of this signal, the Plug and Play card enters the Wait for Key state and all CSNs are reset to 0x00. Power-up values are loaded from non-volatile memory to the configuration registers. The logical device becomes active if the /ACTIV pin is low or if the Activate Register default value in the EEPROM is set to 0x01.
Note: The software must delay 1 msec after RESET_DRV before accessing the auto-configuration ports.
- Config Control Register - The Config Control Register consists of three independent commands which are activated by writing a "1" to their corresponding register bits. These bits are automatically reset to "0" by the hardware after the commands execute.
- Reset command - The Reset command is sent to the Plug and Play cards by writing a value of 0x01 to the Config Control register. All Plug and Play cards in any state, except those in Wait for Key, respond to this command. This command performs a reset function on all logical devices. This resets the contents of configuration registers to their default state. The configuration registers for all logical devices are loaded with their power up values from non-volatile memory. The READ_DATA port, CSN and Plug and Play state are preserved.
- Wait for Key command - The Wait for Key command is sent to the Plug and Play cards by writing a value of 0x02 to the Config Control register. All Plug and Play cards in any state will respond to this command. The CSNs are preserved and no logical device status is changed.
- Reset CSN command - The Reset CSN command is sent to the Plug and Play cards by writing the value of 0x04 to the Config Control register. All Plug and Play cards in any state except Wait for Key will reset their CSN to 0x00.
- Writing 0x07 to the Config Control Register is equivalent to a RESET_DRV event.
Note: The software must delay for 1 ms after the Reset command before accessing the auto-configuration ports.
- Set RD_DATA Port Command - This command is used in the Isolation state and sets the address of the READ_DATA port. Write data bits [7:0] are used as ISA I/O bus address bits[09:02]. The ISA bus address bits[1:0] are fixed at binary "11". The ISA bus address bits[15:10] are fixed at binary `"000000".
Note: After a RESET_DRV or Reset CSN command, this register is considered uninitialized and must be reinitialized.
- Serial Isolation Register - A read from the Serial Isolation Register causes Plug and Play cards in the Isolation state to respond to the ISA bus read cycle.
- Card Select Number - A Card Select Number is uniquely assigned to each Plug and Play card when the card has been isolated and is the only card in the Isolation state. An unidentified card is assigned a value of zero. Valid Card Select Numbers for identified ISA cards range from 1 to 255 and must be assigned sequentially starting from 1. The Card Select Number is used to select a card via the Wake[CSN] command. The Card Select Number on all ISA cards is set to zero on a RESET_DRV or Reset CSN command. The CSN is never set to zero using the CSN register.
- Wake[CSN] Command - This command is used to bring ISA cards in the Sleep state into either the Isolation state or the Configuration state. A Wake[CSN] command with a parameter of zero will force all cards without a CSN to enter the Isolation state. A Wake[CSN] command with a parameter other than zero will force a card with a matching CSN to enter the Configuration state. Any card in the Isolation or Configuration state that receives a Wake[CSN] command with a parameter that does not match its CSN will transition to the Sleep state. All Plug and Play cards function as if their 72-bit serial identifier and their resource data come from a single serial device. The pointer to this data is reset to the beginning whenever a card receives a Wake[CSN] command that has a non-zero CSN value.
- Resource Data Register - One byte of resource data from the Plug and Play card is returned upon a read of this register when in the Configuration state. This data is always returned byte sequentially and the Status register must be read to confirm that resource data is available before the register can be read.
- Status register - Bit[0] of the status register indicates that the next byte of resource data is available to be read. If this bit is one, then data is available, otherwise resource data is not yet available. The Plug and Play software will poll this location until bit[0] is set, then the next data byte from the Resource Data register is read.
- Logical Device Number Register - This register is used to select the logical device on which the configuration commands to follow will operate. The MB86701/701A supports only a single logical device, so this register is not implemented. A read of this register returns 0x00.
- I/O Range Check Register - This register allows the Plug and Play software to determine if another card conflicts with the I/O port range that has been assigned to a logical device. The I/O range check works by having all I/O ranges that would be used by a logical device return 0x55 then 0xAA on I/O read commands. The Plug and Play software performs reads to all the ports that would be used by the logical device and verifies that the correct data is returned. If a conflict is detected, then the Plug and Play software relocates the I/O range of the logical devices a new location. Setting bit[1] of this register enables the I/O range check logic. Setting bit[0] forces the logical device to respond to I/O reads within its assigned I/O range with the value 0x55. If bit[0] is cleared, then the logical device responds to reads within its assigned I/O range with the value of 0xAA. This function operates only when bit[0] of the Activate register is not set.
- Activate register - The Activate register is a read/write register that is used to activate a logical device. An active logical device responds to all ISA bus cycles as allowed by its normal operation. Bit[0] is the activate bit. If it is set to "1" then the logical device is active, otherwise it is inactive.
The MB86701/701A is equipped with a four-bit general purpose I/O port, PIO<3:0>, which can be used to control or monitor external events. Each of these pins can be programmed to be an input or an output. The signal direction is programmed via the I/O Data Direction Register, 0x21. The state of the pin is controlled by writing the data into the I/O Data Register, 0x20 (values for pins programmed as inputs are ignored). Writing a "1" sets the output high, while writing a "0" sets the output low. The current state of the pins can be determined by reading the I/O Data Register.
The PPIC interfaces to the serial EEPROM through a four-wire interface as described in the Signal Descriptions section of this data sheet. The EEPROM is an industry standard 93C56 or equivalent, a 2048-bit device which is internally organized as 128 words by 16 bits (smaller devices in this family can also be used).
It should be noted that the data is internally stored in the EEPROM in a bit-reversed format. That is, the least significant bit of the lower byte of data is stored in the most significant bit of the EEPROM word, while the most significant bit of the upper byte of data is stored in the least significant bit of the EEPROM word, as shown in the example below. This rearrangement of data is not important if the EEPROM is programmed via the PPIC, but must be considered if the EEPROM is programmed by other means.
EEPROM Memory Map
The memory map of the EEPROM is shown in Table 14. Upon reset, an internal pointer to the EEPROM is initialized to address the first word of the EEPROM and the default configuration values (0x000 - 0x015) are read and automatically loaded into the appropriate registers, as detailed in Table 15. In the Isolation state, an additional nine bytes (0x016 - 0x01E, the Plug and Play Serial Identifier) are read from the EEPROM and loaded into an internal shift register for use during the card identification and isolation process. At this point, the internal pointer is pointing to the first byte of the card's resource data structure, 0x01F. When the card enters the Configuration state in response to the card winning the serial isolation protocol and having a CSN assigned, the resource data will be read and used as an input to the resource allocation process performed by the system software. If the card enters the Configuration state directly in response to the Wake[CSN] command, the nine byte serial identifier must be read first before the card's resource data is accessed because the pointer to the Serial EEPROM is reset to 0x16 in response to the Wake[CSN] command where the CSN matches the card's CSN and does not equal zero.
Table 14. EEPROM Memory Map
Notes:
1. Vendor defined data inserted as part of the Resource data must use standard formats per sections 6.2.2.10 and 6.2.3.4. of the PnP specification.
2. Vendor defined data inserted following the End Tag may use any format.
Table 15. Default Register Values in EEPROM
Notes:
1. "Vendor Defined" registers not described in the Plug and Play Specification. See Register Descriptions section of this data sheet.
Reading Data from the EEPROM
In order to read the contents of the EEPROM, the PPIC must be placed into the Configuration State. If this state is entered from the Isolation State, the read address pointer will be pointing to the first byte of the Resource Data, byte 0x1F. If the Configuration State is entered directly from the Sleep State, the read address pointer will be pointing to the first byte of the Serial Identifier, byte 0x016.
The flow chart in Figure 2 outlines the process of reading data from the EEPROM. Data is read sequentially from the Resource Data Register, one byte at a time, starting at the address specified above. Note that the Status Register must be polled before each read of the Resource Data Register to assure that the data from the EEPROM has been obtained and is ready to be read
.
Writing Data to the EEPROM
In order to write data into the EEPROM, the PPIC must be placed into the Configuration State. The PPIC contains a write address pointer which is set to point to address 0x000 in the EEPROM upon reset. Note that this pointer is separate from the read address pointer and is not affected by any EEPROM data read operations.
The flow chart in Figure 3 outlines the EEPROM write process. First, the EEPROM is write enabled. Data is then written sequentially, one word at a time, starting from address 0x000. As a final step, a Write Disable command is sent to the EEPROM to protect the data from any inadvertent writes. Note that a timeout equal to or longer than the specified EEPROM write cycle time (typically 10 ms) is required after the write command for each word of data.
In some applications, there is a FIFO or other local buffer that must be filled or emptied by the driver software. The MB86701/701A provides a special function that can improve system performance in such cases. Figure 4 illustrates the operation of this memory to I/O mapping function, which transforms any access to a specified memory window into an access to a specified I/O address. This allows the user of memory reference instructions such as string or block moves to move the data between the host and the peripheral device. Since these instructions normally execute faster than a loop of I/O reference instructions, system performance is improved.
The function employs the ADD<6:0>, /CS, /READ and /WRITE signals from the PPIC. ADD<6:0> is a value stored in an internal register which is loaded at reset from the default values stored in the EEPROM. It specifies the port offset (1-127) from I/O Base Address 0 and can be located inside or outside the I/O Range associated with that address. /CS is an active low composite chip select which is the logical-OR of IOCS0 and MCS0. MCS0 corresponds to the memory window which is to be mapped into {I/O Base Address 0 + offset} while IOCS0 defines the I/O window for normal I/O register access. While the /IOCS0 portion of /CS is active the ADD<6:0> pins output the ISA bus address from the SA<6:0> inputs and while the /MCS0 portion of the /CS is active these pins output the contents of the offset register. /READ and /WRITE are active low read and write strobes generated by the PPIC. These signals are composed of the /IOR (/IOW) input signal while /IOCS0 and /IOCS1 are active and the /MEMR (/MEMW) signal while /MCS0 is active.
To use this function, connect /CS to the chip select input of the I/O controller, the appropriate number of outputs from ADD<6:0> to the lower address lines, and /READ and /WRITE to the read and write inputs, respectively. Any system access to the window specified by Memory Base Address 0 and its corresponding range will now access the specified I/O register.
Figure 4. Memory to I/O Mapping Function Example
Figures 5 and 6 illustrate typical applications of the MB86701/701A.
In Figure 5, the PPIC is combined with Fujitsu's MB86964 Ethernet controller with Twisted Pair transceiver to form a highly integrated Plug and Play ready Ethernet adapter card. The MB86964 uses one I/O chip select and one interrupt. A memory chip select is used to address the boot PROM or flash memory.
A SCSI controller implementation is shown in Figure 6. Here one I/O chip select and one interrupt are used by Fujitsu's MB86601 SCSI Protocol Controller. The associated dual port FIFO uses /CS, /READ, /WRITE and the ADD outputs to provide the memory I/O mapping function in order to improve data transfer performance between the host and the card. The remaining memory chip select is used to address the boot PROM or flash memory.
Figure 5. Typical MB86701/701A Application - Ethernet Controller
Figure 6. Typical MB86701/701A Application - SCSI Controller
Table 20. Memory Mapping Signal
Timing
ALL SPECIFICATIONS ARE VALID OVER THE RECOMMENDED OPERATING CONDITIONS UNLESS OTHERWISE NOTED.
Table 15. BCLK
Timing
Table 16. Internal Register Read
Cycle
Table 17. Internal Register Write Cycle
Table 18. I/O Chip Select Generation Cycle
Table 19. Memory Chip Select Generation Cycle
Table 21. RESET_DRV Timing
Table 22. IOCHRDY Timing
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ILLINOIS
One Pierce Place, #1130
Itasca, IL 60143-2681
(708) 250-8580
MASSACHUSETTS
1000 Winter Street #2500
Waltham, MA 02154
(617) 487-0029
MINNESOTA
3800 West 80th Street #430
Bloomington, MN 55431-4419
(612) 893-5570
NEW YORK
898 Veterans Memorial Highway
Building 2, Suite 310
Hauppauge, NY 11788
(516) 582-8700
OREGON
15220 N.W. Greenbrier Parkway
#360
Beaverton, OR 97006
(503) 690-1909
TEXAS
14785 Preston Road #274
Dallas, TX 75240
(214) 233-9394
ASIA
HONG KONG
Fujitsu Microelectronics Pacific Asia Ltd.
616-617, Tower B, New Mandarin Plaza
14 Science Museum Road.
Tsimshatsui East,
Kowloon, Hong Kong
Tel: 723-0393
Fax: 721-6555
JAPAN
Fujitsu Limited
Semiconductor Marketing
Furukawa Sogo Building
6-1 Marunouchi, 2-chome
Chiyoda-ku, Tokyo 100, Japan
Tel: 03-3216-3211
Fax: 03-3216-9771
SINGAPORE
Fujitsu Microelectronics PTE Ltd.
51 Bras Basah Road
Plaza by the Park
#06-04/07 Singapore 0718
Tel: 336-1600
Fax: 336-1609
EUROPE
FRANCE
Fujitsu Mikroelektronik GmbH
Europarc
127, Chemin des Bassins
94035 Creteil Cedex, France
Tel: 01-45131212
Fax: 01-45131213
GERMANY
Fujitsu Mikroelektronik GmbH
Am Siebenstein 6-10
6072 Dreieich-Buchschlag, Germany
Tel: 06103-6900
Fax: 06103-690122
Fujitsu Mikroelektronik GmbH
Carl-Zeiss-Ring 11
8045 Ismaning, Germany
Tel: 089-9609440
Fax: 089-96094422
Fujitsu Mikroelektronik GmbH
Am Joachimsberg 10-12
7033 Herrenberg, Germany
Tel: 07032-4085
Fax: 07032-4088
ITALY
Fujitsu Microelectronics Italia, S.R.L.
Centro Direzionale Milanfiori
Strada 4-Palazzo A/2
20094 Assago (Milano), Italy
Tel: 02-8246170/176
Fax: 02-8246189
SWEDEN
Fujitsu Microelectronics Ltd.
Kung Hans vag 12
S-19176 Sollentuna, Sweden
Tel: 08-626-6720
Fax: 08-626-6711
UNITED KINGDOM
Fujitsu Microelectronics, Ltd.
Hargrave House
Belmont Road
Maidenhead
Berkshire SL6 6NE, United Kingdom
Tel: 0628-76100
Fax: 0628-781484