DESCRIPTION

The Fujitsu MB1511 is a single chip serial input PLL frequency synthesizer designed for VHF tuner and cellular telephone applications.

It contains a 1.1 GHz dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time.

It operates supply voltage of 3.0 V typ. and dissipates 7 mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.

The MB1511 is housed in SSOP package, this enables high integration.

Features

S Low power supply voltage: VCC = 2.7 to 5.5 V

S High operating frequency: fIN MAX = 1.1 GHz (VIN MIN = -10dBm)

S Pulse swallow function: 64/65 or 128/129

S Low supply current: ICC = 7 mA typ.

S Serial input 18-bit programmable divider consisting of:
Binary 7-bit swallow counter: 0 to 127
Binary 11-bit programmable counter: 16 to 2047

S Serial input 15-bit programmable reference divider consisting of:
Binary 14-bit programmable reference counter: 8 to 16383
1-bit switch counter (SW) sets divide ratio of prescaler

S On-chip analog switch achieves fast lock up time

S 2 types of phase detector output
On-chip charge pump (Bipolar type)
Output for external charge pump

S Wide operating temperature: -405C to +855C

S 20-pin Plastic Shrink Small Outline Package (Suffix: -PFV)

ABSOLUTE MAXIMUM RATINGS





NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of theis data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS




HANDLING PRECAUTIONS

S This device should be transported and stored in anti-static containers.

S This is static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.

S Always turn the power supply off before inserting or removing the device from its socket.

S Protect leads with a conductive sheet when handing or transporting PC boards with devices.

PIN ASSIGNMENT



PIN DESCRIPTION









Block diagram



Functional Descriptions

1. Pulse swallow function

The divide ratio is set using the following equation.

fVCO = [(M y N) + A] y fOSC P R

fVCO : Output frequency of external voltage controlled oscillator (VCO)

M : Preset modulus of external dual modulus prescaler (64 or 128)

N : Preset divide ratio of binary 11-bit programmable counter (16 to 2047)

A : Preset divide ratio of binary 7-bit swallow counter (0 3 A 3 127, A < N)

fOSC : Output frequency of the external reference frequency oscillator

R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)

2. Serial data input

Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider and 18-bit programmable divider, respectively.

Binary serial data is input to Data pin.

On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit.

Control data "H" data is transferred into 15-bit latch.

Control data "L" data is transferred into 18-bit latch.

(1) Programmable reference divider

Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.



(2) Programmable divider

Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter. Serial 19-bit data format is shown following page.



3. Serial data input timing



Notes: Parenthesis data is used for setting divide ratio of programmable reference divider.
On rising edge of clock shifts one bit of data in the shift register.

4. Phase characteristics

FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level (DO), phase comparator output level (jR, jP) are reversed depending upon FC pin input level. Also, monitor pin (fOUT) output level of phase comparator is controlled by FC pin input level. The relation between outputs (DO, jR, jP) and FC input level are shown below.




NOTE: Z = (High impedance)

Depending upon VCO characteristics, FC pin should be set accordingly:



Phase comparator output waveforms are shown below.



Notes: Phase difference detection range: -2p to +2p
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr>fp or fr<fp, spike might not appear depending upon charge rump characteristics.

5. Analog switch

ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) is connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.




When an analog switch is inserted between LP1 and LP2, faster lock up times is achieved to reduce LPF time constant during PLL channal switching.



ELECTRICAL CHARACTERISTICS (VCC = 2.7 V to 5.5 V, Ta = -405C to +855C)






Notes:

1. fin =1.1 GHz, OSCIN=12 MHz, VCC=3V. Inputs are grounded and outputs are open.

2. AC coupling. Minimum operating frequency is measured when a capacitor 1000pF.

3. VCC=4.0 to 5.5V, 50W

4. VCC=2.7 to 4.0V, 50W

5. VCC=3V

6. VP=VCC to 8V, VOOP=GND to 8V

MEASUREMENT CIRCUIT



TYPICAL APPLICATION EXAMPLE



VPX, VP : 8V max.

C1, C2 : Depends on crystal oscillator

LE, FC : With internal pull up resistor

fP : Open drain output

package dimension



All Rights Reserved.

Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.

The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.

The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications without notice.

This document contains information on a new product. Specification and information herein are subject to change without notice.

No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

FUJITSU LIMITED

For further information please contact:



WFUJITSU LIMITED 1994 SD-08363-01-94