SERIAL INPUT PLL
FREQUENCY SYNTHESIZER
ON CHIP 2.5 GHz PRESCALER
DESCRIPTION
The Fujitsu MB1508 on chip 2.5 GHz dual modulus prescaler is a serial input PLL
(Phase Locked Loop) frequency synthesizer with pulse swallow function. It is well suited for BS tuner, CATV system, and TV tuner applications.
It operates supply voltage of 5.0V typ. and dissipates 16mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
FEATURES
- Power supply voltage: VCC = 4.5 to 5.5V
- High operating frequency: fIN = 2.5 GHz (VIN = -4dBm)
- 2.5 GHz dual modulus prescaler: P = 256/272, 512/528
- Low supply current: ICC = 16mA typ.
- Programmable reference divider consisting of:
Binary 2-bit programmable reference counter (R = 256, 512, 1024, 2048)
- Programmable divider consisting of:
Binary 5-bit swallow counter (A = 0 to 31)
Binary 12-bit programmable counter (N = 32 to 4095)
- Wide operating temperature: -40_C to +85_C
- Plastic 20-pin Flat Package (Suffix: -PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
NOTE: Permanent device damage may occur if the above Absolute Maximum RatIngs are
exceeded.Functional operation should be restricted to the condItions as detailed in the operational
sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
PIN DESCRIPTION
FUNCTIONAL DESCRIPTIONS
DIVIDE RATIO SETTING
Divide ratio can be set using the following equation:
fvco = [(P x N)+ (16 x A] x fosc P R
fvco: Output frequency of external voltage controlled oscillator (VCO)
P: Preset divide ratio of an internal dual modulus prescaler (256 or 512)
N: Preset divide ratio of binary 12-bit programmable counter (32 to 4095)
A: Preset divide ratio of binary 5-bit swallow counter (0 to 31)
fosc: Reference oscillator frequency
R: Preset divide ratio of reference counter (256, 512, 1024, 2048)
SERIAL DATA INPUT
On rising edge of clock shifts one bit of the data into the shift register.
When the load enable is high, the data stored in the shift register is transferred to the latch.
24 bit of serial data format is shown below.
5-BIT SWALLOW COUNTER DIVIDE RATIO (A1 to A5)
12-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (N1 to N12)
FUNCTIONAL DESCRIPTIONS
REFERENCE COUNTER DIVIDE RATIO (R1 to R2)
Prescaler divide ratio (SW)
When divide ratio of prescaler setting bit is high, divide ratio of 256/272 is selected.
When divide ratio of prescaler setting bit is low, divide ratio of 512/528 is selected.
Band Switch Setting (BC1 to BC4)
When band switch setting bit is high, output is ON.
When band switch setting bit is low, output is OFF.
NOTES: On rising edge of the clock shifts one bit of data into the shift register.
When LE is high, the data stored in the shift register is transferred into the latch.
PHASE DETECTOR CHARACTERISTICS
FC pin selects the phase of the phase detector. Phase characteristics (charge pump output) can be reversed depending upon the FC pin input level. Monitor pin (fOUT) output level is selected by FC pin input level as well
.
Note: Z = (High impedance)
VCO CHARACTERISTICS
Depending upon VCO polarity,
FC pin should be set accordingly:
- When VCO polarity are like
FC should be set High or open.
- When VCO polarity are like
FC should be set Low.
PHASE DETECTOR WAVEFORM
NOTES: Phase difference detection range: -2p to +2p
Spike shape depends on charge pump characteristics.
The spike is output to diminish dead band.
RECOMMENDED OPERATING CONDITIONS
Handling Precautions
ELECTRICAL CHARACTERISTICS
NOTE: 1: f in = 2.5GHz, OSCIN=4.0MHz, Vcc=5.0V. Inputs are grounded and outputs are open.
2: AC coupling. Minimum operating frequency is measured with a capacitor 1000pF.
TEST CIRCUIT
Prescaler Input
Sensitivity
MB1508 APPLICATION
CIRCUIT
PACKAGE
DIMENSIONS
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Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given.
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FUJITSU LIMITED
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Japan
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FAX: (069) 6632122
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{ 1991 FUJITSU LIMITED IC-07229-2-91-DS