The Fujitsu CG46 is a high performance, 0.65 mm drawn channel length, digital CMOS gate array family. The CE46 is a 0.65 mm drawn channel length, digital CMOS embedded gate array product family. The CE46 offers full support of diffused high speed RAMs, ROMs and embedded megacells. The CE46 series offers density and performance approaching that achievable with standard cell solutions but with the time to market advantage of traditional gate arrays. Both product families feature channelless (Sea-of-Gates) architecture with two layer metal.
A 5.0 volt product, the CG/CE46 features low power and high pin to gate count ratio. These product families are optimized for cost sensitive, high volume applications such as personal computers, workstations and communication systems. A wide variety of high performance and cost effective packages are available including PQFP, CQFP, TQFP, BGA and MCM's. Pin counts of up to 352 are available.
Features
w 0.65 mm drawn channel length
w 5V $ 5% or 3.3V $ 0.3V supply voltage
w Channelless, Sea-of-gates Architecture
w Internal gate delay of 300ps, F/O = 2, L= 1mm @ 5.0V
w CE46 RAM compiler supports Single/Dual Port RAM
w Supports JTAG boundary scan, full and partial scan
w PCI buffer available
w Clock net for optimized on-chip clock skew control
w High drive capability: 3.2, 8, or 12 mA in a single I/O slot (24 mA available with double I/O)
w Optimized for 5V $5%, capable of 3.3V $0.3V
w Maximum toggle frequency is 175 MHz, Supports system clock frequencies in excess to 70 MHz
w CE46 Supports mixed 5V and 3.3V I/Os
w Supports all major third party design tools including Cadence, Mentor, Synopsys and Sunrise.
w Higher performance and 30% lower power than 0.8 mm technology
w High pad to gate ratio
CE46 Embedded Gate Array Product Summary
CG46 Gate Array Product Summary
DC CHARACTERISTICS
Measuring conditions: VDD = 5V + 5%, Vss = 0 V, Ta = 70 _C
NOTES:
1. VIH = Vdd and VIL = VSS, the memory is in the standby mode
2. If an input buffer with pull-up/pull-down resistor is used, the supply current may not be assured depending on the circuit configuration.
3. The high level output voltage of the IOL=8mA type output buffer is identical to that (IOH = 2mA) of the IOL = 3.2mA type output buffer.
4. If an input buffer with pull-up/pull-down resistor is used, the input leakage current may exceed the above value.
5. Either a buffer without a resistor or with a pull-up/pull-down resistor can be selected from the input and biodirectional buffers.
Absolute Maximum Ratings
NOTES:
1. VSS = 0V
2. For 50 ns max.
3. For one second per pin
Recommended operating conditions (5.0V)
NOTES:
1. VSS = 0V
Recommended operating conditions (3.3 V)
input/output pin capacitance
Measuring conditions: Ta=25 5C
VDD=VI=OV, f=1 MHz
PACKAGE AVAILABILITY
Package Array
CE46 - F10 F20 F30 F40 F50 F60 F70 F80 F90
CG46 - 533 713 833 - 104 - 134 - 194
QFP100 P P P P P
QFP160 P,C P,C P,C P,C P,C P,C P,C P,C P,C
SQFP80 P P P
SQFP100 P P P P
SQFP144 P P P P P P P P
SQFP176 P,C P,C P,C P,C P,C P,C P,C P,C
SQFP208 P,C P,C P,C P,C P,C P,C P,C P,C P,C
SQFP240 P,C P,C P,C P,C P,C P,C P,C P,C
SQFP256 P,C P,C P,C
TQFP100 P P P P P P P P
BGA256(B) P P P P P P
BGA352(B) P1 P1
BGA352(C) P1 P1 P1 P1
NOTES: P: Plastic
C: Cerquad
1: Under Development
DC CHARACTERISTICS at 3.3V Operating Conditions
Measuring conditions: VDD = 3.3V + 0.3V, Vss = 0 V, Ta = 0_ to70 _C
NOTES:
*1. VIH = VDD and VIL = VSS, the memory is in the standby mode.
*2. If an input buffer with pull-up/pull-down resistor is used, the supply current may not be assured depending on the circuit
configuration.
*3. Equivalent to CMOS Input terminal.
*4. Equivalent to CMOS Schmitt Input terminal.
*5. Equivalent to IOL= 3.2mA ouput (at VDD = 5V).
*6. Equivalent to IOL= 8mA ouput (at VDD = 5V).
*7. Equivalent to IOL= 12mA ouput (at VDD = 5V).
*8. Equivalent to IOL= 24mA ouput (at VDD = 5V).
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
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This document contains information on a new product. Specification and information herein are subject to change without notice.
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This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
FUJITSU LIMITED
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WFUJITSU LIMITED 1994 SD-08363-01-94