FOR IMMEDIATE RELEASE
Barry Marsh
Fujitsu Microelectronics, Inc.
(408) 456-1000

Marion Kenefick
(408) 354-1183

New Low-End of FMI's Submicron ASIC Families

SAN JOSE, Calif., Aug. 1, 1995 -- Fujitsu Microelectronics, Inc., a worldwide leader in high-density gate arrays, will begin accepting designs on July 1 for its new 0.65 micron 5V CG46/CE46 CMOS ASIC product family. The CG46/CE46 Series, developed for mainstream ASIC design, features an excellent pin-to-gate ratio, Ball Grid Package (BGA) support, and up to 73,000 usable gates in a channelless 'sea-of-gates' architecture.

Power consumption, at 4mW/gate, is more than 30 percent lower than in Fujitsu's 0.8 micron CMOS ASIC product families, according to Barry Marsh, director of ASIC marketing for FMI. Overall performance of the CG46 0.65 micron family will be significantly higher for designs using between 24,000 and 73,000 gates.

Average gate utilization is approximately 45 percent. I/O pads range from 208 to 400. The companion CE46 is an embedded array family that supplies complete support of diffused high-speed RAMs and ROMs. Chip-to-chip clock synchronization is managed by internal phase locked loops.

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FOR FURTHER INFORMATION:

Betsy Taub
Fujitsu Microelectronics, Inc.
(408) 922-9440

Dick Davies
Independent Public Relations Assoc.
(415) 777-4161


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