Note: All descriptions apply to both MB86961 and MB86961A unless otherwise noted.
Additional features in MB86961A only
The MB86961(A) Universal Interface for 10BASE-T
(Twisted-Pair) Ethernet is fully compliant with the IEEE
802.3 specifications for AUI (Attachment Unit Interface)
and 10BASE-T (Twisted-Pair) interfaces and provides
the electrical interface between an Ethernet controller
and the DB15 (AUI) and RJ45 (10BASE-T) connections
to an Ethernet local area network. Functions provided by
the MB86961(A) include Manchester encoding and
decoding of the serial data stream, level conversion,
collision detection, signal quality error (SQE) and link
integrity testing, jabber control, loopback, and automatic
correction of polarity reversal on the twisted-pair input.
Pulse shaping and filtering functions are performed by the MB86961(A) to eliminate the need for external filtering components and thus reduce overall system cost. The device also provides outputs for receive, transmit, collision and link test LEDs and provides compatibility with both shielded and unshielded twisted pair cables. The receive threshold can be reduced to allow an extended range between nodes in low noise environments. Its wide range of features and its ability to interface to virtually all popular controllers make the MB86961(A) the ideal device for twisted pair Ethernet applications.
The MB86961(A) is part of a complete family of Ethernet devices available from Fujitsu. It is fabricated in a low-power CMOS technology and is supplied in a 44-pin PLCC package.
PIN CONFIGURATION
SIGNAL DESCRIPTIONS
SIGNAL DESCRIPTIONS (Continued)
Figure 1 shows the MB86961 (A) in a typical application,
interfacing between a controller and the RJ45 connector
of the twisted-pair network. Figures 2 through 5 show
detailed diagrams of various MB86961 (A) applications.
AUTO PORT SELECT LOOPBACK
CONTROL PIN
With MD0 and MD1 both tied high, the MB86961 (A) logic and framing are set to Mode 4 (compatible with National NS8390 controllers).
The AUTOSEL pin is tied high, allowing the MB86961 (A) to automatically select the active port. The high at LI enables Link Testing.
The UTP and NTH pins are both tied high selecting the standard receiver threshold and 100 W termination for unshielded TP cable. (See Figure 2.)
MANUAL PORT SELECT LINK
TEST FUNCTION
With MD0 low and MD1 tied high, the MB86961 (A) logic and framing are set to Mode 3 (compatible with Fujitsu MB86950 an MB86960 controllers). As in Figure 2, the LI pin is tied high, enabling Link Testing, and the UTP and NTH pins are both tied high, selecting the standard receiver threshold and 100 W termination for unshielded TP cable. However, in this application AUOTSEL is tied low, allowing external port selection through the PAUI pin. The remote status output are inverted and used to drive LED indicators. (See Figure 3.)
TWISTED-PAIR ONLY
Figure 4 shows the MB86961 (A) is a typical twisted-pair only application. The DTE is connected to a 10BASE-T network through the twisted-pair RJ45 connector. (The AUI port is not used.) With MD0 tied high and MD1 grounded, the MB86916 (A) logic and framing are set to Mode 2 (compatible with Intel 82586 controllers). The LI pin externally controls the link test function. The UTP and NTH pins are both tied low., selecting the reduced receiver threshold and 150 W termination for shielded TP cable. The switch at lEDT/PDN manually controls the power down mode. (See Figure 4.)
AUI ENCODER/DECODER ONLY
In this application the DTE is connected to at coaxial network through the AUI. AUTOSEL and PAUI are both tied to ground, manually selecting the AUI port. The twisted-pair port is not used. With MD1 and MD0 both grounded, the MB86961 (A) logic and framing are set to Mode 1 (compatible with AMD AM7990 controllers). The LI pin is tied low, disabling the link test function. The LBK input controls loopback. A 20 MHz crystal connected across CLKI and CLK0 provides the required clock signal. (See Figure 5.)
The MB86961(A) Universal Ethernet Interface
Transceiver performs the physical layer signaling (PSL)
and Media Attachment Unit (MAU) functions as defined
by the IEEE 802.3 specification. It functions as a
PLS-only device (for use with 10BASE2 or 10BASE5
coaxial cable networks) or as an Integrated PLS/MAU
(for use with 10BASE-T twisted-pair networks).
The MB86961(A) interfaces a back-end controller to either an AUI drop cable or twisted-pair (TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data output (DO), Data Input (DI) and Collision (CI). The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the MB86961(A) contains an internal crystal oscillator and four LED drivers for visual status reporting.
Functions are defined from the back end controller side of the interface. The MB86961(A) Transmit function refers to data transmitted by the back end to the AUI cable (PLS-Only mode) or to the twisted-pair network (Integrated PLS/MAU mode). The MB86961(A) Receive function refers to data received by the back end from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the MB86961(A) performs all required MAU functions defined by the IEEE 802.3 10BASE-T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control and loopback. In the PLS-Only mode, the MB86961(A) receives incoming signals from the AUI DI circuit with up to 18ns of jitter and drives the AUI DO circuit.
CONTROLLER COMPATIBILITY MODES
The MB86961(A) is compatible with most industry standard controllers including devices produced by Advanced Micro Devices (AMD), Intel, Fujitsu and National Semiconductor. Four different control signal timing and polarity schemes (Modes 1 through 4) are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller compatibility modes as listed in Table 1.
Table 1. MB86961(A) Compatibility Modes
The related timing specifications are provided in the electrical characteristics section of this data sheet.
TRANSMIT FUNCTION
The MB86961(A) receives NRZ data from the controller
at the TXD input (see MB86961(A) block diagram), and
passes it through a Manchester encoder. The encoded data
is then transferred to either the AUI cable (the DO circuit)
or the twisted-pair network (the TPO circuit). The
advanced integrated pulse shaping and filtering network
produces the output signal on TPON and TPOP, shown in
Figure 6. The TPO output is pre-distorted and prefiltered
to meet the 10BASE-T jitter template. No external filters
are required. During idle periods, the MB86961(A)
transmits link integrity test pulses on the TPO circuit if LI
is enabled and integrated PLS/MAU mode is selected.
The MB86961(A) can be programmed for either shielded
TP (150 W) or unshielded TP (100 W) through the UTP
pin.
JABBER CONTROL FUNCTION
Figure 7 is a state diagram of the MB86961(A) Jabber control function. The MB86961(A) on-chip watchdog timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and activates the JAB pin. Once the MB86961(A) is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 seconds before it will exit the jabber state.
SQE FUNCTION
In the integrated PLS/MAU mode, the MB86961(A) supports the signal quality error (SQE) function as shown in Figure 8. After every successful transmission on the 10BASE-T network, the MB86961(A) transmits the SQE signal to the DTE for 10 +5 bit times over the internal CI Circuit.
RECEIVE FUNCTION
The MB86961(A) receive function acquires timing and data from the twisted-pair network (the TPI circuit) or from the AUI (the DI Circuit). Valid received signals are passed through the on-chip filters and Manchester
decoder and output as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively. No external filters are required.
An internal intelligent squelch function discriminates noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the MB86961(A) receive function enters the idle state. If the polarity of the TPI circuit is reversed, the MB86961(A) detects the polarity reversal and reports it via the PLR output. The MB86961(A) automatically corrects reversed polarity.
POLARITY REVERSE FUNCTION
The MB86961(A) polarity reverse function uses both link pulses and end-of-frame data to determine the polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the MB86961(A) enters the link fail state
and no valid data or link pulses are received within 96 to 128 ms the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled.
COLLISION DETECTION FUNCTION
The collision detection function operates on the
twisted-pair side of the interface. A collision is defined
as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The MB86961(A) reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 9 is a state diagram of the MB86961(A) collision detection function. Refer to Electrical Characteristics for collision detection and COL/CI output timing.
LOOPBACK FUNCTION
The MB86961(A) provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the MB86961(A) from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. The "normal" loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber states.
The MB86961A also provides three additional loopback functions. An external loopback mode, useful for system-level testing, is controlled by pin 21 (LEDC). When LEDC is tied low, the LXT901 disables the collision detection and internal loopback circuits, to allow external loopback. (This function is not implemented in the MB86961(A).) The MB86961(A) provides additional loopback functions controlled by pin 22 (LBK). When the TP port is selected and LBK=1, TP loopback is "forced," overriding collisions on the TP circuit. When LBK=0, normal loopback is in effect.
When the AUI port is selected and LBK=1, data
transmitted by the back-end is internally looped back
from the TXD pin through the Manchester
encoder/decoder to the RXD pin. When LBK=0, no AUI
loopback occurs.
LINK INTEGRITY TEST
Figure 10 is a state diagram of the MB86961(A) Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when pin 8 (LI) is tied high. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50-150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The MB86961(A) ignores any link integrity pulse with an interval less than 2-7 ms. The MB86961(A) will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses.
REMOTE SIGNALING
The MB86961(A) transmits standard link pulses which
meet the 10BASE-T specification. However, the
MB86961(A) encodes additional status information into
the link pulse by varying the link pulse timing. This is
referred to as remote signaling. Using alternate pulse
intervals, the MB86961(A) can signal three local
conditions: link down, jabber, and remote signaling
capability. Figure 11 shows the interval variations used to
signal local status to the other end of the line. The
MB86961(A) also recognizes these alternate pulse
intervals when received from a remote unit. Remote
status conditions are reported to the controller over the
RLD, RJAB and RCMPT output pins.
ABSOLUTE MAXIMUM RATINGS
1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
INPUT/OUTPUT CHARACTERISTICS (TA = 0_C to +70_C, VCC = 5 V +5%)
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
2. Limited functional test patterns are performed at these input levels. The majority of functional tests are performed at levels 0V and 3 V.
AUI ELECTRICAL CHARACTERISTICS (TA = 0_C to +70_C, VCC = 5 V +5%)
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
TP ELECTRICAL CHARACTERISTICS (TA = 0_C to +70_C, VCC = 5 V +5%)
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
2. Parameter is guaranteed by design, not subject to production testing.
SWITCHING CHARACTERISTICS (TA = 0_C to +70_C, VCC = 5 V +5%)
1. Parameter is guaranteed by design; not subject to production testing.
RCLK/Start-of-Packet Timing
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
RCLK/End-of-Packet Timing
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
2. CD Turn off delay measured from middle of last bit, so timing specification is unaffected by the value of the last bit.
Transmit Timing
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.
Collision Detection, COL/CI Output and Loopback Timing
1. Typical figures are at 255 C and are for design aid only; not guaranteed and not subject to production testing.