The MB86933H is the default owner of the bus.





























PACKAGE THERMAL CHARACTERISTICS




DC SPECIFICATIONS3 VCC = 5V + 5%





*1 Note: Use ICC (typ) values to calculate maximum case and ambient temperature allowed. Note that maximum junction temperature of die is 1255C. For example, Allowed ambient temp = 1255C.- (ICC)  (5.25V)  jJA

AC CHARACTERISTICS1,2,4 VCC = 5V + 5%









AC CHARACTERISTICS1,2,4 VCC = 5V + 5%






1. Parameters are valid over specified temperature range and supply voltage range unless otherwise noted.

2. All voltage measurements are referenced to ground. All time measurements are referenced at input and output levels of 1.5V. For testing, all inputs swing between 0.4V and 2.4V (Except XTAL1 which swings from 0.4V to 3.0V). Input rise and fall times are 2ns or less.

3. Not more than one output may be shorted at a time for a maximum duration of one second.

4. Timing specifications apply to frequency of operation listed at top of column.

5. All output timings are based on a 50pF load.

7. These specs will be improved in the future.

8. Data bus output driver control is same as for RD/-WR so timing is similar.









Interrupt Signal, Interrupt Input Width




1. In HIGH Level or RISING-EDGE trigger mode, if this width is satisfied, the interrupt request FLIP-FLOP is set.

2. In LOW Level or FALLING-EDGE trigger mode, if this width is satisfied, the interrupt request FLIP-FLOP is set.





SPARC is a registered trademark of SPARC International based on technology developed by Sun Microsystems, Inc.

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w 20 MHz (50ns/cycle) operating frequency

w SPARC[ V8 high-performance RISC architecture

w 1 KByte, direct mapped instruction cache

w Flexible locking mechanism for instruction cache

w 6 window, 104 word register file

w Fast interrupt response time

w 16 address spaces, 256 MByte each

w User and supervisor modes

w Data write buffer and instruction prefetch buffer

w On-chip programmable chip selects and wait-state generators

w Support for 8-, 16-, and 32-bit wide external memory

w On-chip DRAM controller for glue-less connection to DRAM

w On-chip interrupt controller

w On-chip clock generator circuit

w JTAG test interface

w Single vector trapping

w 0.8 micron gate, 3-level metal CMOS technology

w 160-pin QFP MB86933-compatible pinout



The MB86933H is targeted toward applications which require a high-performance, low-cost processor with high integration. The CPU is based on the SPARC V8 architecture, is code compatible with previous implementations, and is pin compatible with the MB86933. At 20 MHz, the processor executes at 20 MIPs peak and 18 MIPs sustained performance.

Included to maximize the performance of the system are a large register file, a 1KByte instruction cache, a data write buffer, and an instruction prefetch buffer.

Included to minimize external glue logic are chip-select outputs, programmable wait-state generators, an interrupt controller, and a complete DRAM controller. Also included is the ability to program each chip select region for different external data bus widths (8/16/32-bit). See MB86933H block diagram on page 3.

These features combine to allow the MB86933H to offer high performance and SPARC compatibility at a low cost to make it the right choice for a wide range of cost-sensitive, performance-oriented embedded designs.



PIN CONFIGURATION



PIN ASSIGNMENT - 160-PIN QFP




ORDERING CODE




Note: The ordering code for production level product. Early shipments of this device may be marked with "ES" to indicate that the part is not yet at full production status. Contact your local Fujitsu representative for additional information on "ES" level products.

BLOCK DIAGRAM



SIGNAL DESCRIPTIONS















The Fujitsu MB86933H is a high-performance, 32-bit RISC processor which executes at 20 MIPs peak and 18 MIPs sustained performance with 20 MHz clock frequency. Like its predecessors, the MB86933H is based on the SPARC V8 architecture and is upward code compatible with previous implementations. More importantly, the MB86933H has been developed specifically with the needs of embedded applications in mind and offers high performance and low cost for these applications.

The MB86933H instruction set is streamlined and hardwired for fast execution with most instructions executing in a single cycle. The Integer Unit (IU) features a 5-stage pipeline which has been designed to handle data interlocks, has an optimized branch handler for efficient control transfers, and a bus interface to handle single cycle bus accesses to on-chip memory.

KEY FEATURES

Fast Instruction Execution: Simple functions make up the bulk of instructions in most programs so that execution speed can be greatly improved by designing these instructions to execute in as short a time as possible. The majority of instructions execute in one cycle with only a few of the more complex, such as integer multiply, taking additional cycles.

On-chip Instruction Cache: To decouple the speed of the processor from the memory subsystem a 1 KByte direct mapped instruction cache is included on chip. It is possible to individually lock lines in the cache to ensure deterministic response and higher performance for critical or frequently recurring routines.

Large Register Set: The large register set (104 registers) reduces the number of required accesses to data memory. The registers are organized into six overlapping groups called register windows which allows registers to be reserved for high priority tasks, such as interrupts, or for recurring requirements such as operating system working registers. The overlapping windows also simplify parameter passing during procedure linkage and reduce code in most programs.

Hardware Multiplier: The MB86933H also includes hardware for integer multiply. The hardware support significantly improves the performance of these operations with 32-bit integer multiplies executing in 5 clock cycles, 16-bit integer multiplies in 3 cycles, 8-bit integer multiplies in 2 cycles, and a multiply by zero can complete in a single cycle.

Interrupt Controller: An on-chip interrupt controller is provided on the MB86933H. Four interrupt pins can either be programmed to act as an encoded external interrupt vector providing for up to 15 interrupts or as four individual interrupt lines.

Bus Interface: The requirement for glue logic between the MB86933H and the system is removed by providing programmable chip selects and programmable wait-state circuitry. Each chip select region can be programmed to support either 8-bit, 16-bit, or 32-bit wide memory. Multiple bus masters are supported through a simple handshake protocol.

Instruction Prefetch Buffer: A one-word prefetch buffer is provided to increase performance when instruction cache misses occur.

Data Write Buffer: A one-word write buffer is provided to decouple writes from internal instruction execution. Data can be posted to the write buffer and execution from internal cache can continue in parallel while the store completes to external memory.

DRAM Controller: Present on the MB86933H is a complete DRAM controller which provides glueless connection to up to two banks of DRAM memory. Support for either 16-bit or 32-bit wide DRAM memory banks is provided.

Clock Generator: To simplify the clock design a crystal can be connected directly to the on-chip oscillator or an external clock source can be used. A built-in phase-locked loop minimizes the skew between on- and off-chip clocks.

Enhanced Instruction Set: An integer divide-step instruction cuts divide times by a factor of 10 over previous SPARC implementations. A scan instruction supports a single cycle search for the most significant 1 or 0 in a word.

Fully Static Circuit Design: Embedded applications that need a means to reduce power consumption can take advantage of the MB86933H's fully static design. The processor clock can be slowed or stopped for arbitrary periods of time to reduce operating current with no loss of internal state. Noise immunity is improved as well. (Note: stopping the clock will result in the Phase-Locked Loop losing lock. Lock must be re-established before normal operation can be resumed.)

Test and Debug Interface: The MB86933H supports production test through industry standard JTAG boundary scan.

CPU

The MB86933H core is a high-performance full-custom implementation of the SPARC V8 architecture. The core is compact to leave room for peripheral integration and yet is designed in a way to allow the major blocks to be customized for varying application requirements. The core is made up of three functional units: the Instruction block, the Address block and the Execute block. (See Figure 1.)

A five-stage instruction pipeline is responsible for decoding all instructions and generating the control signals to the other blocks. The 5-stage pipeline consists of Fetch (F), Decode (D), Execute (E), Memory (M) and Writeback (W). Instruction memory is addressed and returns instructions in the (F) stage, the register file is addressed and returns operands in the (D) stage, the ALU computes results in the (E) stage, external memory is addressed in the (M) stage, and the register file is written back in the (W) stage.

ADDRESS SPACE

The MB86933H offers a large addressing range and allows separate user and supervisor spaces to be defined. In addition to 28 address lines, 4 alternate address space identifiers (ASIs) distinguish between protected and unprotected space. Of the 16 possible ASI values, two define accesses to user data and user instruction space while the remaining ASI values define supervisor space.

Anytime a reset, synchronous trap or asynchronous trap occurs, the processor is placed into the supervisor mode. In this mode, the processor executes instructions and moves data out of supervisor space. While in supervisor

mode, the processor also has access to the remaining ASI values. Except for those mentioned and those reserved for control register space, the remaining ASI values can be used to access other alternate data spaces defined by the application.

The distinction of user versus supervisor space allows the hardware to protect against accidental or un-authorized access to system resources. For real-time operating system (RTOS) development for example, the separate spaces provide a mechanism for effectively partitioning RTOS space from user space.

TABLE 1. MB86933 Instruction Set



REGISTERS



The MB86933H register set is divided into those used for general-purpose functions and those used for control and status.

The 104 general-purpose registers are divided into 6 global registers and 6 overlapping blocks or "windows". Each window contains 24 registers. Of these, 8 are local to the window, 8 "out" registers overlap with the next window and 8 "in" registers overlap with the previous window. (See Figure 2.)

This organization makes it easy to pass parameters to subroutines. Parameters that are to be passed along are written to the "out" registers and the subsequent procedure call decrements the window pointer to make a new set of registers available. The passed parameters are now available to the subroutine in the current window's "in" registers.

Register windows improve performance in embedded applications because they function as local variable caches which retain either interrupt, subroutine, context or operating system variables with no additional overhead. In addition, code can be reduced by exploiting the efficient execution of procedure linkage by preventing in-lining compiler optimizations.

The registers that make up the register file each have three read-only and one write-only port. The use of a four-port register file allows even store instructions, which may require that three operands be read out of the register file, to proceed at one instruction per cycle.

The control and status registers include those defined by the SPARC architecture (see Table 1) and those mapped into alternate address space to control peripheral functions (see Table 2).

INSTRUCTION SET

The MB86933H is upward code compatible with other SPARC V8 processors. Additional instructions, previously not directly supported, have been added to improve performance in embedded applications. Integer multiply, integer divide step, and scan for first changed bit have been added to the already powerful SPARC instruction set. See Table 1 for a list of supported instructions.



INTERRUPTS



A key measure of a processor's suitability for use in embedded application is in its ability to handle interrupts with a minimum of delay and in a deterministic fashion. The MB86933H implementation has been tailored to insure not only low average latency but low maximum latency as well.

Interrupt response time is made up of the sum of the times it takes the processor to finish its current task after recognizing an interrupt, and the time it takes to begin executing interrupt service routine instructions. The MB86933H implements numerous features to minimize both factors.

To minimize the time it takes to finish the current task, the MB86933H is designed so that tasks can either be interrupted or completed in a minimum number of cycles. Implementation details that accomplish this aim include an integer divide operation that is interruptible through the use of a divide step instruction and a fast multiply operation to minimize non-interruptible instruction execution.

To minimize the time required to start executing the interrupt service routine the processor switches to a new register window when an interrupt is detected. This feature allows the service routine to be executed without first requiring that the current registers be saved.

INTERRUPT CONTROLLER

The SPARC V8 architecture, and the MB86933H in particular, provides for up to 15 separate external interrupt sources. The MB86933H has four external interrupt pins and an on-chip interrupt controller (IRC) which can support two modes of operation.

Mode 0 (IRL mode): In mode 0 the input on the four external pins is interpreted as an encoded interrupt vector. This mode allows for external logic to generate any one of the 15 possible interrupts ("0" represents "no interrupt request"). In this mode of operation it is assumed that the external interrupt source maintains the interrupt vector on the pins until it is explicitly cleared by writing to an external memory mapped location. Note that this mode is the same as that on the MB86930/932/933 and is compatible with the MB86940 companion chip.

Mode 1 (IRQ mode): In the mode 1 the four pins are considered to be four separate interrupt sources mapping to interrupts 12 through 15. Note this mode is the same as that on the MB86931

Figure 3 shows a block diagram of the IRC in mode 1.

The Trigger Mode Control logic selects one of four trigger modes for each of the four channels: high level, low level, rising edge, or falling edge. The processor controls the triggers by writing to the Trigger Mode register.

The IRQ latch captures each of the four interrupt requests. The system processor reads the latch via the Request Sense register and clears the latch by writing to the Request Clear register. The example assembly language program below shows the code sequence for writing to the Request Clear register of channel 12.





The IRQ Mask logic allows selective masking of the interrupts. The processor controls masking by writing to the Mask register.

The Priority Encoder prioritizes the interrupt requests and encodes the highest priority pending interrupt that is not masked. pin IRL3 maps to interrupt 15, IRL2 maps to interrupt 14, IRL1 maps to interrupt 13 and IRL0 maps to interrupt 12.

The IRL latch captures the encoded interrupt level number that is generated by the priority encoder.

INSTRUCTION CACHE

The MB86933H has an on-chip, 1KByte, direct-mapped, sectored instruction cache. The line length of the cache is 16 bytes. Lines are subdivided into four sub-blocks, each four bytes wide. On a cache miss, the cache is updated in sub-block increments. Also, on a cache miss the instruction prefetch buffer fetches the next sequential anticipating that it will be needed to fill then next instruction cache miss.

The cache can be used in either normal mode or one of two lock modes.

Global locking allows the entire content of the instruction cache to be frozen. A bit in the cache control register enables or disables global locking.

Local locking makes it possible to dynamically lock selected instructions on a line-by-line basis. This feature gives the flexibility, for example, to assure deterministic response for certain critical routines by locking the routine's code into the cache while still allowing other locations to be used as a cache. Note, however, that because the cache is direct-mapped, code which would normally map into the locked cache locations will not be cached.

BUS INTERFACE

The Bus Interface Unit (BIU) is designed to simplify the interface between the MB86933H and the rest of the system. Separate address and data buses make de-multiplexing unnecessary. Simple control signals make it easy to build fast systems.

The BIU includes two features to increase performance when accessing external memory - an instruction prefetch buffer to support efficient instruction fetches and a write buffer to support data writes.



A key measure of a processor's suitability for use in embedded application is in its ability to handle interrupts with a minimum of delay and in a deterministic fashion. The MB86933H implementation has been tailored to insure not only low average latency but low maximum latency as well.

The BIU also includes circuitry to enable the design of complex systems with a minimum requirement for external glue logic. The bus interface unit supports up to six regions of memory - each region with independently programmable wait-state generation, chip select generation, and programmable bus widths. This allows for the support of multiple width memories within a single system. There is also included a complete DRAM controller for glueless connection to DRAM.

Prefetch Buffer

Associated with the instruction cache and the BIU is a one-word prefetch buffer. After an instruction fetch which misses in the cache has been satisfied, the prefetch buffer will immediately initiate another instruction access to the next sequential address. Instructions are prefetched only when the BIU does not have another pending request for a bus transaction (eg. a write to memory).

Write Buffer

Also associated with the BIU is a one-word write buffer. For stores this buffer effectively hides the external memory latency. When a store occurs the data is posted to the write buffer. The IU can then continue to execute from internal cache while the write buffer completes the store to external memory.

Chip Selects

As on the other 930 Series chips, there are six chip selects. Each chip select can be associated with a region of memory and will determine the characteristics for that region. Associated with each chip select is a wait state generator which can be set to internally terminate an external memory access after a preprogrammed number of cycles. Also associated with each chip select (except chip select 0) are control bits which determine the external bus width. The bus width for each memory region can be set to 8-bit, 16-bit or 32-bit.

Chip select 0 is dedicated for boot code. It can be programmed to be 8-bit, 16-bit, or 32-bit wide based on two external pins: BMODE8_ and BMODE16_. When the DRAM controller is used, chip select 4 is dedicated for the DRAM controller support. It should be noted that while on previous 930 Series family members the "samepage" circuitry could be associated with any chip select, on the MB86933H "samepage" is specifically associated with chip select 4.

Byte, halfword, and word operations are supported on all bus widths (8-, 16-, and 32-bit). It should be noted that all loads (byte, halfword, word) return a total of 32 bits (possibly with multiple accesses) regardless of the width of the bus. This is done to be compatible with other 930 Series family member where the minimum granularity of the on-chip data cache is one word.

DRAM Controller

The MB86933H provides all the necessary logic to directly connect up to 16 MB of fast page-mode DRAM without external glue logic (or 128 MB with external buffers). Address multiplexing is performed internally and the DRAM row and column addresses (MA<11:0>) are output on the ADR<27:16> pins. Two -RAS lines allow access to up to two banks of memory. Each -RAS signal controls a bank of memory. Each bank is configurable in both depth and width. The width can be programmed to be either 32-bit wide or, for low cost systems, 16-bit wide. Four -CAS signals allow for byte, halfword, and word stores to memory. Each -CAS signal controls a byte in a 32 bit word. -CAS0 controls accesses to byte 0, etc. Internal "samepage" detect logic is provided to allow for a minimum 2-cycle samepage access to the DRAM. An internal refresh timer is used to generate a -CAS before -RAS refresh cycles automatically at programmable intervals. The -DWE (DRAM Write Enable) pins determines whether a read or write access is being made to DRAM.

DRAM configurations supported by the MB86933H:




where n = 1, 4, 8, 16



CLOCK GENERATOR

The on-chip clock generator provides a means to directly connect the MB86933H to either a crystal oscillator or an external clock source. For either case, the external frequency is the same as the chip operating frequency.

A clock output signal provides the system with a reference by which external timing can be synchronized when not using an external clock source. The skew between the internal clock and an external input clock source is minimized by the inclusion of an on-chip phase lock loop circuit.

TABLE 1. MB86933 Control and Status Registers (All registers are read/write)



TABLE 2. MB86933 Memory Mapped Control Registers (All registers are read/write)



TABLE 2. MB86933 Memory Mapped Control Registers (All registers are read/write) (Continued)







The Bus Interface Unit (BIU) has the logic which allows the MB86933H to interface with the system. The system interface is made up of the address and data buses, the interrupt request bus and various control signals. The BIU is either handling requests for external memory operations, arbitrating for bus access, or idle.

Operation of the BIU

In the case of a write to external memory, the BIU makes use of a write buffer which can hold a one-word write transaction. When the BIU receives a request for a write transaction it stores the write data and address in the write buffer allowing the IU to continue operating out of on-chip instruction cache. The BIU then proceeds to complete the write to external memory. In most cases the write buffer will hide external memory latency from the IU. The exceptions are in cases where the write buffer is still filled from a previous transaction or if the subsequent IU cycle results in an instruction cache miss. In these cases, IU execution is held until the write buffer is emptied.

The BIU includes a one-stage prefetch buffer for instruction fetches. This buffer is used to fetch the next sequential instructions after an instruction cache miss. The instruction is prefetched only if the BIU does not have a request for a bus transaction from the IU nor is any external device requesting use of the bus. The prefetch buffer operation is suspended if the buffer is full. This occurs if the prefetched instruction is a hit in the instruction cache. The buffer restarts after another instruction cache miss. If an exception occurs during an instruction prefetch, the exception is not sent to the IU unless the instruction is actually requested by the IU. The prefetch buffer operates only when the instruction cache in enabled.

Exception Handling

The external memory system can indicate an exception during a memory operation. The BIU signals the appropriate data or instruction exception to the IU which will trap accordingly.

Bus Cycles

Timings 1 through 19 illustrate representative combinations of bus cycles.

Load

Regardless of the external bus size (8, 16, or 32 bits), all instruction fetches and loads (including load byte and load half word) retrieve a 32-bit quantity. This is done for compatibility with 930 Series processors with data cache where the smallest granularity in the cache is one word.
Bus sizes can be programmed based on chip select regions to be 8, 16, or 32 bit wide.

Load (32-bit wide bus)

Whenever a load from data memory is requested or an instruction cache miss occurs, the BIU performs a read from external memory (see Timing 1).

With a 32-bit external data bus, a read transaction begins with the BIU asserting -AS, to indicate a new bus transaction. The -AS signal is de-asserted after one cycle. At the same time the ADR< 27:2 > and ASI< 3:0 > bits are driven with the location to be read. The BIU drives the RD/-WR signal high to indicate a read transaction. Since all loads retrieve 32 bits, -BE<0:3> are not used when the bus is 32-bit wide and are all driven low.

The external memory system responds with the read data on pins D< 31:0 >. It also asserts the -READY signal when the data is ready. For slow memory, the -READY signal can be delayed until data is valid.

A load double operation is treated as back-to-back reads.

Load (16-bit wide bus)

When the bus is programmed to be 16 bits wide (defined by the chip select region) every load will retrieve 32-bits. Timing 2. shows a load (Byte, half word, word) operating with an 16-bit bus. For the ldb and ldh the IU masks off the bits which are not required. For a 16-bit bus the -BE<2> pin is defined to be the ADR<1> address bit. -BE<2> as well as BE<0:1> are unused and are driven low.

Load (8-bit wide bus)

When the bus is programmed to be 8 bits wide (defined by the chip select region) every load will retrieve 32-bits. Timing 3. shows a load (Byte, half word, word) operating with an 8-bit bus. For the ldb and ldh the IU masks off the bits which are not required. For a 8-bit bus -BE<2:3> are the ADR<1:0> address bits. -BE<0:1> are unused and are driven low.

Load with Exception

If the external memory system sees a memory exception it can terminate the current memory transaction by asserting the -MEXC and -READY signals. The data on the data bus is ignored by the MB86933H.

Store

Unlike loads, stores are sized to programmed bus size and require only the minimum number of bus cycles to complete the store. For example, only two bus cycles are required to do a sth on a 8-bit bus.

Store (32-bit wide bus)

A write transaction begins with the BIU asserting -AS, to indicate a new bus transaction. The -AS signal is de-asserted after one phase. At the same time the ADR < 27:2 > and ASI < 3:0 > pins are driven with the location to be written while the D < 31:0 > pins has corresponding write data. The -BE<0:3> are the high to low order byte enables, respectively and indicate which bytes to write for a given type of store operation (byte, half-word or word ). The BIU drives the RD/-WR signal low to indicate a write transaction.

The external memory system responds by asserting the -READY signal when it has stored the data. Or, if the internal wait state generator is enabled, -READY is generated internally to the MB86933H.

A store double operation is treated as back-to-back writes. (see Timing 5.)

Store (16-bit wide bus)

Stores to 16-bit memory are sized to the bus. That is, for a 16-bit bus, a store word requires two cycles while a store halfword or store byte requires a single cycle. Timing 6., 7., 8. show the timing for different types of stores. For a 16-bit bus, the -BE<2> is defined to be ADR<1>. -BE<3> is unused and is driven low. -BE<1:0> are defined to be the high and low order byte enables, respectively.

Store (8-bit wide bus)

Stores to 8-bit memory are sized to the bus. That is, for an 8-bit bus, a store word requires four cycles, a store halfword requires two cycles, and store byte requires a single cycle. Timing 9., 10., 11. show the timing for different types of stores. For a 8-bit bus, the -BE<2:3> are defined to be ADR<1:0>. -BE<1:0> are unused and are driven low.

Store with Exception

If an access exception occurs on a write, the external memory system can terminate the current memory transaction by asserting the -MEXC and -READY signals. The external memory system is expected to ignore the data on the data bus in this situation.

Atomic Load Store

An atomic load store executes as a load followed by a store with no operation allowed in between. The -LOCK signal is asserted to indicate that the bus is being used for more than one external memory operation.

There is one cycle between the termination of the read and the beginning of the write to provide time for the switching of the data bus drivers.

DRAM Bus Timings

During a DRAM access the row and column address,are output on ADR<27:16> pins. Timing diagram 14 shows 2 back-to-back DRAM reads which are not in the same page. Timing 15 shows a DRAM write followed by a DRAM read, again not in the same page. Timing 16 shows both samepage reads and writes. Note that the BIU always inserts an idle cycle in between a read and a write. Timing 17 shows a read followed by a refresh. The on-chip timer is used as a refresh counter.

External Bus Request and Grant

Any external device can request ownership of the bus by asserting the -BREQ signal. The BIU asserts the -BGRNT signal to indicate that it is relinquishing control of the bus and also three-states all of its bus drivers. In the following cycle, the external device can complete its transaction. On completion of its transaction the external device de-asserts the -BREQ signal. The BIU responds by de-asserting the -BGRNT signal in the following cycle.