DESCRIPTION

The Fujitsu CG51/CE51 is a series of ultra high performance CMOS gate arrays. The CG51 is a high density Sea-of-Gates array for applications requiring high levels of integration or low power. The CE51 is a high performance embedded gate array family offering full support of diffused high speed RAMS, ROMS and embedded megafunctions. The CE51 series offers density and performance approaching that achievable with standard cell solutions with the time-to-market advantage of a gate array.

True 3V products, the CG51/CE51 feature very low power (1.2 microwatt/Mhz) and both 3.3V and 5.0V compatible I/Os. These advanced product families are targeted at users who are seeking very high performance or very high levels of integration. Potential end-user applications include computers, supercomputers, workstations, graphic terminals, telecom networking, and signal processing.

FEATURES

S 0.5 Micron Drawn Channel Length

S Triple layer metal

S 3.3V + 0.3V supply voltage

S Chanelless, Sea-of-gates Architecture

S Internal gate delay of 210ps, F/O = 2, L = 1mm

S Low power consumption: 1.2 microwatt/gate/Mhz

S Maximum toggle frequency: 600Mhz

S High speed I/Os: PCML (PECL), LVTC

S Supports 3.3V and 5.0V I/O

S RAM compiler supports Single/Dual/Triple port RAM

S Supports JTAG boundary scan, full and partial scan

S Phase Locked Loop for interchip clock skew control

S Clock net for optimized on-chip clock skew control

S Advanced packaging options include QFP, PGA, BGA, and MCM

S High drive capability: 2, 4, 8, 12, or 24mA

S Supports all major third party EDA tools including: Cadence, Mentor, Synopsys



PRODUCT SUMMARY





DC CHARACTERISTICS

Measuring conditions: VDD = 3.3V + 0.3V,VSS = 0V, Tj = -0 to 1005C









NOTES:

1. When VIH = VDD and VIL = VSS, memory is in the standby mode.

2. If an input buffer with pull-up/pull-down resistor is used, the supply current may not be assured depending on the circuit configuration.

3. 5V interface is only for CMOS level.

4. If an input buffer with pull-up/pull-down resistor is used, the input leakage current may exceed the above value.

5. Either a buffer without a resistor or with a pull-up/pull-down resistor can be selected from the input and bidirectional buffers.

6. Maximum supply current at the short-circuit of output and VDD or VSS.

ABSOLUTE MAXIMUM RATINGS





* VSS = 0V

RECOMMENDED OPERATING CONDITIONS





* VSS = 0V

THIRD PARTY EDA TOOL SUPPORTED

Fujitsu supports an "openCAD" environment allowing an ASIC designer the widest possible range of design options. Both the CG51 gate array and CE51 embedded array product families are fully supported by Fujitsu's ASIC management environment (FAME). FAME runs on leading workstations and provides a seamless link from loading third party ASIC design tools to Fujitsu's ASIC back end environment. FAME provides management functions, translation utilities, design rule checking and full back annotation capabilities. FAME fully supports all leading third party tools including Simulation, Design Synthesis, Test and Layout tools.

Currently supported tools include:

Cadence: Verilog-XI 1.6c, Veritime 1.3

Mentor: Design Architect 8.2, Autologic 8.2, QuickSim II 8.2, QuickPath 8.2

Synopsys: Design Analyzer 2.2b/3.0, VSS 2.2a/3.0

Sunrise Systems: ATPG

IKOS Logic and Fault Simulator IKOS 5.04c

Zycad: Logic and Fault Simulator Xplus 5.1a

PACKAGE OPTIONS

In addition to offering plastic and ceramic versions of industry standard packages such as PQFPs and PGAs, Fujitsu also offers an impressive array of advanced packaging technology. Our long experience with high speed logic and thermal management has led us to develop some of the most advanced packaging available anywhere. From cost effective, single chip packages to sophisticated multichip modules, Fujitsu has a packaging option to suit your requirements. Whether you need a 208 PQFP, the newest in high I/O count surface mounted Ball Grid Array (BGA) packages or full custom packaging we can deliver the optimal solution.

Packaging Options

343 114 164 214 284 364 484 654 754

Quad Flat Package (1.0, 0.8, 0.65 mm pin pitch)

64 P

80 P

100 P1

120 P,C C

160 P,C P,C P,C P,C P,C P,C P,C

196 P,C P,C P,C P,C C

232 C P,C P,C C

Shrink Quad Flat Package (0.5 mm pin pitch)

64 P

80 P

100 P P P P

120 P

144 P1 P P P

176 P,C P,C P,C P,C P,C

208 P1,C P1,C P,C P,C P,C P,C P,C

240 P1,C1 P1,C P1,C P,C P,C P,C

256 P1,C1 P1,C P1,C P1,C P1,C

304 C1 C1 C C C

Fine Pitch Flat Package (0.4 mm pin pitch)

304 C1 C1 C1 C

Pin Grid Array Package

256 C C C C C

299 C1 C C C C

321 C1 C C C

361 C C C

401 C1 C1 C C

Ball Grid Array (BGA)

256 P P P

352 P P

416 P1 P1

576 P1

NOTES: 1 : Under Development
C : Ceramic Package
P : Plastic Package

FRONT-END DESIGN FLOW

CLOCK SKEW CONTROL

To maximize performance in high speed, high density arrays, a designer must maintain tight clock skew control. In addition to an available PLL to manage interchip clock skew, Fujitsu's clock driven design methodology (CDDM) offers accurate on chip clock skew control. CDDM offers accurate RC extraction of clock tree parameters, interactive clock tree implementation, simplifies trade-offs between clock tree delay and clock skew, early verification of potential design hold time errors and race conditions.



All Rights Reserved.

Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given.

The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.

The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu.

Fujitsu reserves the right to change products or specifications without notice.

This document contains information on a new product. Specification and information herein are subject to change without notice.

No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Electronic Devices International
Sales and Engineering Support Division
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FUJITSU MICROELECTRONICS, INC.
Logic Products Division
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FAX: 408-432-9044

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WFUJITSU LIMITED 1994 SD-08363-01-94