The new MB86936, now available in samples, includes a glueless interface to DRAM, SRAM, and ROM; configurable bus sizing so it can accommodate 8-bit, 16-bit or 32-bit memories; and an 8-bit video rasterization interface. These new features enhance other notable capabilities of the 930 RISC embedded Series, including line lockable caches and an on-board floating point unit, which was introduced in an earlier version of the series, the MB86934.
The 936 is designed with a 4 Kbyte instruction cache and a 2 Kbyte data cache, both of which are set-associative. The two caches allow the IC to decouple efficiently from external memory latency.
It also is constructed with an expanded 3-channel DMA controller that can use the processor bus even if the integer unit of FPU execute out of cache. Internal operation of the MB86936 is 3.3V; I/O can be operated at 3V or 5V. With clock doubling, the processor operates at 50 MHz; peak execution is 50 MIPs. The half-speed bus facilitates use of less expensive memories and reduces overall system cost.
Debug and diagnostic support also is included on the MB86936, so it can be connected directly to hardware emulators, providing non-intrusive debug even at 50 MHz. Code migration is simplified because the IC is compatible with version 8E of the SPARC architecture. Popular third party software tools will be ready by the first calendar quarter of 1996.
The MB86936 is the latest version of FMI's RISC 930 Series, originally introduced in 1991, and also including the low-end, low-cost MB86933H, which costs less than $20 each in production quantities. The MB86936 is manufactured using Fujitsu's 0.5 micron, 3-level metal CMOS technology. Prices begin at $90 each in samples. Production begins in early 1996.