DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH GHz PRESCALER
DESCRIPTION
The Fujitsu MB1510 is a 1.1 GHz dual serial input PLL (Phase Locked Loop) frequency synthesizer designed for cellular telephone and cordless telephone
applications.
The MB1510 has two PLL circuits on a single chip: PLL1 and PLL2. An analog switch is provided for each PLL circuit decrease lock up time. Separate power supply pins are provided for each PLL circuit as well.
1.1 GHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates from a supply voltage of 3.0V typ. and dissipates 15 mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
FEATURES
ABSOLUTE MAXIMUM RATINGS (see NOTE)
NOTE: Permanent device damage may occur if the above Absolute MaxImum Ratings are exceeded.
Functional operation should be restricted to the conditions as detailed in the operational sections
of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
PIN DESCRIPTIONS
PIN DESCRIPTIONS (Continued)
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fvco = {(M x N) + A} x fosc P R (A < N)
fvco: Output frequency of external voltage controlled oscillator (VCO)
M: Preset divide ratio of dual modulus prescaler (64 or 128)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0 3 A 3 127)
fosc: Reference oscillation frequency
R: Preset divide ratio of reference counter (512 or 1024)
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider of PLL1 section and programmable divider of PLL2 section are controlled individually.
Serial data of binary data is input into Data pin.
On rising edge of clock shifts one bit of serial data into the shift register. When load enable signal is high. the data stored in the shift register is transferred to either the latch of PLL1 section or the latch of PLL2 section depending upon the control bit data setting.
SHIFT REGISTER CONFIGURATION
N1 to N11 : Divide ratio of the programmable counter setting bit (16 to 2047)
A1 to A7 : Divide ratio of the swallow counter setting bit (0 to 127)
FC : Phase control bit of the phase detector
PRE : Divide ratio of the prescaler setting bit (64/65,128/129)
FP : Output of the programmable divider control bit (fp1 or fp2)
REF : Divide ratio of the reference counter setting bit (512 to 1024)
CHT : Control bit
SERIAL DATA INPUT
TIMING
On rising edge of the dock shifts one bit of the data into the shift register.
BlNARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Note: Divide ratio loss than 16 is prohibited.
Divide ratio (H) range = 16 to 2047
BlNARY 7-BIT SWALLOW COUNTER DATA SETTING
Note: Divide ratio (A) range = 0 to 127
PRE : DlVlDE RATlO (P) OF THE PRESCALER SETTING BlT
H =64/65
L=128/129
REF : DlVlDE RATlO (R) OF THE REFERENCE COUNTER SETTING BlT
H=S12 (fr=25.0 kHz)
L= 1024 (fr= 12.5 kHz)
FP: OUTPUT OF THE PROGRAMMABLE DlVlDER SETTING BIT
H = fp pin (15 pin) outputs programmable~ divider output frequency (fp1) of PLL1 section.
L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of PLL2 section5
FC : PHASE CONTROL BlT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.
Note: Z = High-impedance
Depending upon the VCO polarity,
FC should be bit set.
PHASE DETECTOR OUTPUT
WAVEFORM
Note: Phase difference detection range = 32p to +2p
LD output becomes low when phase difference is tW or more.
LD output becomes high when phase difference less than tW is repeated 3 times or more.
(e. g. tW = 625 to 1250ns, foscin = 12.8 MHz)
Spike appearance depends on the charge pump characteristics. The spike is output to diminish the dead band.
When fr > fp or fr < fp, spike might not generate depending on the charge pump characteristics.
ANALOG SWITCH
ON/OFF of the analog switch is controlled by BSC input signal. BSC1 controls the analog switch of the PLL1 circuit, BSC2 controls the analog switch of PLL2. When the analog switch is ON, BS pin output the charge pump output (D01, D02). When analog switch is OFF, BS pin is set to high-impedance.
When an analog switch is inserted between LPF-1 and LPF-2, faster lock up time is achieved to reduce LPF time constant during PLL
channel
switching.
RECOMMENDED OPERATING CONDITIONS
HANDLING PRECAUTIONS
ELECTRICAL CHARACTERISTICS
Notes: *1: Divide ratio of the prescaler is 128/129.
*2: Divide ratio of the prescaler is 64/65.
TEST CIRCUIT (PRESCALER INPUT SENSITIVITY
TEST)
APPLICATION
EXAMPLE
Note: X'tal: 1 2.8MHz
C1, C2: depends on the crystal oscillator.
Clock, Data, LE: involve the schmitt circuit
When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation.
PACKAGE
DIMENSIONS
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Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete Information sufficient for construction purposes is not necessarily given.
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